Task scheduling and voltage selection for energy minimization

Hu, Xiaobo Sharon; Chen, Danny Z.

doi:10.1145/513965.513966

Cited by 72 publications

(107 citation statements)

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“…Zhang et al [17] used the same real-time model as we do (weighted directed acyclic graphs (DAGs) with deadlines). They did not use EDF scheduling but scheduled in such a way to have more slowdown opportunities.…”

Section: Related Workmentioning

confidence: 99%

Leakage-Aware Multiprocessor Scheduling

Langen

Juurlink

2008

J Sign Process Syst Sign Image Video Technol

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When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however, static power consumption due to leakage current is expected to increase significantly. Then it will be more effective to limit the number of processors employed (i.e., turn some of them off), or to use a combination of DVS and processor shutdown. In this paper, leakage-aware scheduling heuristics are presented that determine the best trade-off between these three techniques: DVS, processor shutdown, and finding the optimal number of processors. Experimental results obtained using a public benchmark set of task graphs and real parallel applications show that our approach reduces the total energy consumption by up to 46% for tight deadlines (1.5× the critical path length) and by up to 73% for loose deadlines (8× the critical path length) compared to an approach that only employs DVS. We also compare the energy consumed by our scheduling algorithms to two absolute lower bounds, one for the case where all processors continuously run at the same frequency, and one for the case where the processors can run at different frequencies and these frequencies may change over time. The results show that the energy reduction achieved by our best approach is close to these theoretical limits.

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Section: Related Workmentioning

confidence: 99%

Leakage-Aware Multiprocessor Scheduling

Langen

Juurlink

2008

J Sign Process Syst Sign Image Video Technol

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“…As our work is devoted to developing power aware scheduling algorithms for dependent tasks, we compare our work with related research in this topic. [26], [23], [27], [24], [25] schedule dependent tasks on real time, where the tasks normally are assigned with arrival time, deadline and max power consumption. In our research of energy aware high end computing, we don't have these restrictions on the tasks to be scheduled.…”

Section: Power Aware Task Schedulingmentioning

confidence: 99%

Towards Energy Aware Scheduling for Precedence Constrained Parallel Tasks in a Cluster with DVFS

Wang

Laszewski

Dayal

et al. 2010

2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing

189

108

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Abstract-Reducing energy consumption for high end computing can bring various benefits such as, reduce operating costs, increase system reliability, and environment respect. This paper aims to develop scheduling heuristics and to present application experience for reducing power consumption of parallel tasks in a cluster with the Dynamic Voltage Frequency Scaling (DVFS) technique. In this paper, formal models are presented for precedence-constrained parallel tasks, DVFS enabled clusters, and energy consumption. This paper studies the slack time for non-critical jobs, extends their execution time and reduces the energy consumption without increasing the task's execution time as a whole. Additionally, Green Service Level Agreement is also considered in this paper. By increasing task execution time within an affordable limit, this paper develops scheduling heuristics to reduce energy consumption of a tasks execution and discusses the relationship between energy consumption and task execution time. Models and scheduling heuristics are examined with a simulation study. Test results justify the design and implementation of proposed energy aware scheduling heuristics in the paper.

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“…Common to these approaches is that when PV-DVS is applied for power reduction, it is applied to one task (tile) at a time and is done after assignment and scheduling. Zhang et al [79] and Varatkar and Marculescu [80] proposed using a list scheduling algorithm to find an initial task schedule, and the DVS problem was solved by integer linear programming. The idea behind these methods is to maximize the available slack in a schedule so as to enlarge the solution space of using DVS.…”

Section: Energy-aware Taskmentioning

confidence: 99%

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2011

Journal of Electrical and Computer Engineering

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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

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Task scheduling and voltage selection for energy minimization

Cited by 72 publications

References 0 publications

Leakage-Aware Multiprocessor Scheduling

Leakage-Aware Multiprocessor Scheduling

Towards Energy Aware Scheduling for Precedence Constrained Parallel Tasks in a Cluster with DVFS

Networks on Chips: Structure and Design Methodologies

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