TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism

Chronaki, Kallia; Casas, Marc; Moretó, Miquel; Bosch, Jaume; Badía, Rosa M.

doi:10.1007/978-3-319-92040-5_20

Cited by 4 publications

(5 citation statements)

References 26 publications

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“…The granularity is then a balance between the degree of parallelism and the RS overhead. For that reason, several researches are conducted to delegate partially or totally the RS system to the hardware with the objective of relieving the worker threads, as in Chronaki et al (2018).…”

Section: Task-based Parallelizationmentioning

confidence: 99%

Increasing the degree of parallelism using speculative execution in task-based runtime systems

Bramas

2019

PeerJ Computer Science

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Task-based programming models have demonstrated their efficiency in the development of scientific applications on modern high-performance platforms. They allow delegation of the management of parallelization to the runtime system (RS), which is in charge of the data coherency, the scheduling, and the assignment of the work to the computational units. However, some applications have a limited degree of parallelism such that no matter how efficient the RS implementation, they may not scale on modern multicore CPUs. In this paper, we propose using speculation to unleash the parallelism when it is uncertain if some tasks will modify data, and we formalize a new methodology to enable speculative execution in a graph of tasks. This description is partially implemented in our new C++ RS called SPETABARU, which is capable of executing tasks in advance if some others are not certain to modify the data. We study the behavior of our approach to compute Monte Carlo and replica exchange Monte Carlo simulations. Subjects Distributed and Parallel ComputingHow to cite this article Bramas B. 2019. Increasing the degree of parallelism using speculative execution in task-based runtime systems. PeerJ Comput. Sci. 5:e183 http://doi.org/10.7717/peerj-cs.183 Bramas (2019), PeerJ Comput. Sci., DOI 10.7717/peerj-cs.183 2/25 Bramas (2019), PeerJ Comput. Sci., DOI 10.7717/peerj-cs.183 3/25 ALGORITHM 2: Replica Exchange Monte Carlo (parallel tempering) simulation algorithm. 1 function REMC(domains[N], temperature[N]) 2 // Compute energy (particle to particle interactions) 3 for s from 1 to N do 4 energy[s] ← compute_energy(domains[s]) 5 end 6 // Iterate for a given number of iterations 7 for iter from 1 to NB_LOOPS_REMC do 8 for s from 1 to N do 9 // Compute usual MC for each simulation 10 MC_Core(domains[s], temperature[s], energy[s]) 11 end 12 // Compare based on a given strategy 13 for s in exchange_list(iter) do 14 // Use the energy difference between s and s+1 to decide to exchange them 15 if random_01() ≤ metropolis(energy[s] -energy[s+1], temperatures[s]) then 16 swap(domains[s], domains[s+1]) 17 swap(energy[s], energy[s+1]) 18 end 19 end 20 end Bramas (2019), PeerJ Comput. Sci., DOI 10.7717/peerj-cs.183 6/25 Thachuk C, Shmygelska A, Hoos HH. 2007. A replica exchange Monte Carlo algorithm for protein folding in the HP model. BMC Bioinformatics 8(1):342 Nikolopoulos DS. 2018. A taxonomy of task-based parallel programming technologies for highperformance computing. The Journal of Supercomputing 74(4):1422-1434. Tillenius M. 2015. Superglue: a shared memory framework using data versioning for dependency-aware task-based parallelization. SIAM Journal on Scientific Computing 37(6):C617-C642 X. 2013. Parallel metropolis coupled Markov chain Monte Carlo for isolation with migration model. Applied Mathematics & Information Sciences 7(1L):219-224 DOI 10.12785/amis/071L30.

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Section: Task-based Parallelizationmentioning

confidence: 99%

Increasing the degree of parallelism using speculative execution in task-based runtime systems

Bramas

2019

PeerJ Computer Science

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“…Chronaki et al [31] study how to efficiently assign task to cores in asymmetric multiprocessor systems by exploiting the critical path of the TDG. Moreover, the same authors target the bottleneck of task creation and dependence analysis by offloading the TDG construction to an already existing specialized hardware and studying how the runtime controls this hardware [30]. LibPRISM [93] is used to autotune the prefetcher policy and SMT levels in OpenMP parallel applications by profiling online the parallel regions or task characteristics..…”

Section: Exploiting Runtime System Information In the Architecturementioning

confidence: 99%

Parallel architectures and runtime systems co-design for task-based programming models

Castillo Villar

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The increasing parallelism levels in modern computing systems has extolled the need for a holistic vision when designing multiprocessor architectures taking in account the needs of the programming models and applications. Nowadays, system design consists of several layers on top of each other from the architecture up to the application software. Although this design allows to do a separation of concerns where it is possible to independently change layers due to a well-known interface between them, it is hampering future systems design as the Law of Moore reaches to an end. Current performance improvements on computer architecture are driven by the shrinkage of the transistor channel width, allowing faster and more power efficient chips to be made. However, technology is reaching physical limitations were the transistor size will not be able to be reduced furthermore and requires a change of paradigm in systems design. This thesis proposes to break this layered design, and advocates for a system where the architecture and the programming model runtime system are able to exchange information towards a common goal, improve performance and reduce power consumption. By making the architecture aware of runtime information such as a Task Dependency Graph (TDG) in the case of dataflow task-based programming models, it is possible to improve power consumption by exploiting the critical path of the graph. Moreover, the architecture can provide hardware support to create such a graph in order to reduce the runtime overheads and making possible the execution of fine-grained tasks to increase the available parallelism. Finally, the current status of inter-node communication primitives can be exposed to the runtime system in order to perform a more efficient communication scheduling, and also creates new opportunities of computation and communication overlap that were not possible before. An evaluation of the proposals introduced in this thesis is provided and a methodology to simulate and characterize the application behavior is also presented. El aumento del paralelismo proporcionado por los sistemas de cómputo modernos ha provocado la necesidad de una visión holística en el diseño de arquitecturas multiprocesador que tome en cuenta las necesidades de los modelos de programación y las aplicaciones. Hoy en día el diseño de los computadores consiste en diferentes capas de abstracción con una interfaz bien definida entre ellas. Las limitaciones de esta aproximación junto con el fin de la ley de Moore limitan el potencial de los futuros computadores. La mayoría de las mejoras actuales en el diseño de los computadores provienen fundamentalmente de la reducción del tamaño del canal del transistor, lo cual permite chips más rápidos y con un consumo eficiente sin apenas cambios fundamentales en el diseño de la arquitectura. Sin embargo, la tecnología actual está alcanzando limitaciones físicas donde no será posible reducir el tamaño de los transistores motivando así un cambio de paradigma en la construcción de los computadores. Esta tesis propone romper este diseño en capas y abogar por un sistema donde la arquitectura y el sistema de tiempo de ejecución del modelo de programación sean capaces de intercambiar información para alcanzar una meta común: La mejora del rendimiento y la reducción del consumo energético. Haciendo que la arquitectura sea consciente de la información disponible en el modelo de programación, como puede ser el grafo de dependencias entre tareas en los modelos de programación dataflow, es posible reducir el consumo energético explotando el camino critico del grafo. Además, la arquitectura puede proveer de soporte hardware para crear este grafo con el objetivo de reducir el overhead de construir este grado cuando la granularidad de las tareas es demasiado fina. Finalmente, el estado de las comunicaciones entre nodos puede ser expuesto al sistema de tiempo de ejecución para realizar una mejor planificación de las comunicaciones y creando nuevas oportunidades de solapamiento entre cómputo y comunicación que no eran posibles anteriormente. Esta tesis aporta una evaluación de todas estas propuestas, así como una metodología para simular y caracterizar el comportamiento de las aplicaciones

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“…ISC 2018. [15] The publication presents the design and requirements of a hardware manager to accelerate the task management in the software runtimes.…”

Section: Thesis Publications and Contributionsmentioning

confidence: 99%

“…ISC 2018. [15] In this work, the DDAST implementation has been used to characterize the software runtime overheads and define the hardware manager requirements.…”

Section: Publicationsmentioning

confidence: 99%

Breaking host-centric management of task-based parallel programming models

Pons¹

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Heterogeneous platforms had become popular to increase the computational power of the systems within a constrained power budget. They are present in several systems, from embedded platforms and mobile devices to high-end servers and clusters. However, the co-processors are managed following a master-slave model where the general-purpose CPU drives the rest of elements. This management limits the system possibilities as not all application parts are suitable to be executed in an accelerator. This thesis presents different proposals to enhance the usage of co-processors in task-based parallel programming models, which are a powerful tool to easily program applications for heterogeneous platforms. The first proposal enhances the task-based systems with an asynchronous, concurrent, and parameterizable behavior. The improvements go across the full-stack, from the programming model level down to the low-level communications used between the libraries and the co-processors. The evaluation shows that the implemented improvements boost the applications' performance as they can be easily tuned for the running platform. The second proposal adds support for task spawn and synchronization in co-processors. The offloaded tasks can create child tasks that target other architectures or remain inside the co-processor. This allows the programmers to implement applications easily and effectively. The evaluation shows the efficiency of the proposal implementation in terms of latency and power consumption. The results show that applications can increase their performance and optimize their power consumption just moving the task spawn from the host threads to the co-processor. This is thanks to the low-latency task management inside the co-processors, which also reduces the communications between the host and the co-processor. The third proposal extends task-based programming models with concepts of recurrent workloads. The regular task syntax has been extended with new clauses to label the recurrent tasks and provide the needed information to the runtime. The evaluation shows an application programmability increase thanks to the new syntax, which allows the specification of recurrent systems with much less code and better accuracy. Also, the direct management of task repetitions and periods in the co-processors allows an almost zero-latency management that is able to manage any task granularity. Els sistemes heterogenis s'han popularitzat, ja que permeten incrementar la potència de càlcul sense implicar un augment del consum energètic. Aquests sistemes van des de plataformes encastades i dispositius mòbils, fins a servidors i clústers d'altes prestacions. En tots ells, la gestió dels coprocessadors segueix el patró primari-secundari on la unitat de còmput general (CPU, per les seves sigles en anglès) dirigeix la resta d'elements. Aquesta gestió limita les possibilitats dels sistemes i limita les parts de les aplicacions que poden ser executades en els acceleradors. Aquesta tesi presenta diferents propostes per millorar l'ús dels coprocessadors dins dels models de programació paral·lels basats en tasques. Aquests models de programació són una eina molt potent que permet programar fàcilment aplicacions pels sistemes heterogenis. La primera proposta millora els models de programació basats en tasques mitjançant aproximacions asíncrones, concurrents i parametritzables. Les millores són a tots els nivells, des del model de programació fins a les comunicacions a baix nivell entre les llibreries i els coprocessadors. Els resultats de l'avaluació mostren que les millores augmenten el rendiment de les aplicacions perquè permeten adaptar-les fàcilment a les plataformes d'execució. La segona proposta afegeix suport per la creació de tasques i la seva sincronització dins dels coprocessadors. Les tasques enviades als coprocessadors poden crear tasques filles pel mateix coprocessador o per altres elements del sistema. Això flexibilitza i facilita la programació d'aplicacions. L'avaluació mostra l'eficiència de la proposta respecte a la latència i el consum d'energia. Els resultats revelen que les aplicacions poden incrementar el seu rendiment i optimitzar el seu consum energètic creant les tasques directament a dins dels coprocessadors. La millora es deu a la baixa latència de la gestió de tasques dins dels coprocessadors que també suposa una reducció de les comunicacions entre la CPU i el coprocessador. La tercera proposta amplia les capacitats dels models de programació basats en tasques introduint conceptes de sistemes recurrents. La sintaxi bàsica d'una tasca s'amplia amb noves clàusules per distingir les recurrents i proporcionar al runtime la informació necessària. L'avaluació de la proposta mosta una millora en la programabilitat de les aplicacions gràcies a la nova sintaxi. Aquesta permet la creació de sistemes recurrents amb menys codi i amb una precisió major. La gestió directa de les repeticions i períodes de les tasques recurrents dins dels coprocessadors resulta en una latència mínima que permet qualsevol granularitat de tasques.

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TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism

Cited by 4 publications

References 26 publications

Increasing the degree of parallelism using speculative execution in task-based runtime systems

Increasing the degree of parallelism using speculative execution in task-based runtime systems

Parallel architectures and runtime systems co-design for task-based programming models

Breaking host-centric management of task-based parallel programming models

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