TCAD-Based Predictive NBTI Framework for Sub-20-nm Node Device Design Considerations

Mishra, Subrat; Wong, Hiu Yung; Tiwari, Ravi; Chaudhary, Ankush; Rao, Rakesh; Moroz, Victor; Mahapatra, S.

doi:10.1109/ted.2016.2615163

Cited by 26 publications

(6 citation statements)

References 23 publications

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“…Some statistical reliability models were proposed for FinFET and SRAM cells and used to investigate the NBTI effects [16]. An NBTI framework for 20 nm node devices was presented by Mishra et al [17]. The stress generated by BTI is found to be more significant than PBTI stress.…”

Section: State-of-the-art Bti Modelsmentioning

confidence: 99%

“…NBTI reduces the inversion charges and degrades the electron and hole mobility. It is due to the Coulomb scattering and depends on the applied gate voltage, temperature, and stress time [16,17]. In these works, they also assumed that the generated interface state is designing a substrate gate interface bond with their energy distribution.…”

Section: State-of-the-art Bti Modelsmentioning

confidence: 99%

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Design and Development of BTI Model and 3D InGaAs HEMT-Based SRAM for Reliable and Secure Internet of Things Application

2020

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It is broadly accepted that the silicon-based CMOS has touched its scaling limits and alternative substrate materials are needed for future technology nodes. An Indium-Gallium-Arsenide ( I n G a A s )-based device is well situated for further technology nodes. This material also has better mobility of the electrons and holes for the high performance and real-time system design. The improved mobility helps to increase the operating frequency of the device which is useful for Internet of Things (IoT) applications. However, I n G a A s -based High Electron Mobility Transistors (HEMT) limits the reliability of the device due to the presence of dangling bonds at the channel–gate insulator interfaces. Weak dangling-bonds get broken under electric stress, and positive hydrogen atoms are trapped into the oxide. This charge trapping depends on the material parameters and device geometry. In this paper, the existing Bias-Temperature-Instability (BTI) model is modified based on the material parameters and device geometry. Charge trapping and annealing constants are the most critical BTI model parameters that are modeled and evaluated based on different HEMT material parameters. The proposed model was compared to experimental and TCAD simulation results. The proposed model has been used for lifetime prediction of the InGaAs HEMT-based Static Random-Access Memory (SRAM) cell because it is used to store and process the information in the IoT applications.

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Section: State-of-the-art Bti Modelsmentioning

confidence: 99%

Section: State-of-the-art Bti Modelsmentioning

confidence: 99%

Design and Development of BTI Model and 3D InGaAs HEMT-Based SRAM for Reliable and Secure Internet of Things Application

2020

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“…However, it has been recently shown [17,18] that trap generation obtained from the double interface H-H 2 reaction-diffusion (RD) model, when augmented with the transient trap occupancy model as well as hole trapping in preexisting defects, can accurately predict measured stress and recovery data under wide range of experimental conditions. Therefore, in this Letter, the device characteristics are simulated in ATLAS [19][20][21] and the double interface H-H 2 RD model has been implemented for simulation of degradation during NBTI stress [22]. NBTI in SLBS PMOS was analysed and compared with bulk and FD SOI using ATLAS (physically based device simulation software) [23].…”

Section: Device Structure and Simulationmentioning

confidence: 99%

Negative bias temperature instability in SOI‐like p‐type metal oxide semiconductor devices

Shan

Wang

et al. 2018

Micro & Nano Letters

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A silicon on insulator (SOI)-like bulk silicon (SLBS) MOSFET has been recently reported. An 'n/p-/n+' structure was contained in SLBS P Metal Oxide Semiconductor (PMOS) device, with 'p-' is made of 4H-SiC. This player is fully depleted. In this work, negative bias temperature instability (NBTI) of SLBS pMOSFET is studied and compared with that in bulk and Fully Depleted (FD) SOI PMOSFET. The effects of stress temperature and body bias on NBTI of SLBS device are also be studied in this work. The work demonstrates an advantage of SLBS over bulk and FD SOI devices.

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“…Cross-sectional TEM pictures of FinFET structures are presented in Figure 3. The technology process and device characteristics' descriptions were published in [13][14][15][16][17], and TCAD modeling and simulation results were published in [18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

Comparative Characterization of NWFET and FinFET Transistor Structures Using TCAD Modeling

2022

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A complete comparison for 14 nm FinFET and NWFET with stacked nanowires was carried out. The electrical and thermal performances in two device structures were analyzed based on TCAD simulation results. The electro-thermal TCAD models were calibrated to data measured on 30–7 nm FinFETs and NWFETs. The full set of output electrical device parameters Ion, Ioff, SS, Vth, and maximal device temperature Tmax was discussed to achieve the optimum VLSI characteristics.

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TCAD-Based Predictive NBTI Framework for Sub-20-nm Node Device Design Considerations

Cited by 26 publications

References 23 publications

Design and Development of BTI Model and 3D InGaAs HEMT-Based SRAM for Reliable and Secure Internet of Things Application

Design and Development of BTI Model and 3D InGaAs HEMT-Based SRAM for Reliable and Secure Internet of Things Application

Negative bias temperature instability in SOI‐like p‐type metal oxide semiconductor devices

Comparative Characterization of NWFET and FinFET Transistor Structures Using TCAD Modeling

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