TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks

Abstract

In-Memory Computing (IMC), which takes advantage of analog multiplication-accumulation (MAC) insides memory, is promising to alleviate the Von-Neumann bottleneck and improve the energy efficiency of deep neural networks (DNNs). Since the time-domain (TD) computing is also an energy-efficient analog computing paradigm, we present an 8kb mixed-signal IMC macro, TD-SRAM, by combining IMC with TD computing. A dual-edge single input (DESI) TD computing topology is proposed, which can significantly improve the area and power efficiencies of TD cell. The TD-SRAM bitcell consisting of a 6T DESI based TD cell and a 6T-SRAM cell supports binary DNNs. In the IMC mode, 60 columns work in parallel and 96-input binary-MAC operations are processed in each column. Implemented in a standard 40-nm CMOS process, the TD-SRAM achieves the high energy efficiency of 537 TOPS/W at 0.9-V supply. With different DNN topologies, the test chips achieve the accuracy of 95.90%-98.00% with a dual 2-bit time-to-digital converter (TDC) in the MNIST dataset.

Memristive Devices for Time Domain Compute-in-Memory

“…we have demonstrated read disturb stability for binary devices under constant read voltage pulses for up to 5x10 10 VMM operations suggesting that far larger numbers of read operations are possible than conventionally investigated for memory applications under the right conditions. For this stability, the SET voltage has to be kept below -0.3 V and the RESET voltage has to be kept below 0.5 V. While short read pulses can be expected for cascaded TDCIM, further investigations must be made on read disturb, as shape and duration of the read pulse heavily depend on circuit implementation.…”

“…All cells can implement unrolled kernels to allow for minimal memory movement. While [10] provides a small footprint when scaled, its delay element only consists of a single current starved inverter, leading to low SNR. For the sake of comparability, a version of the design was considered, that queues multiple delay stages, scaling the SNR by √ N scale .…”

“…4c by assuming 8track cell height corresponding to used technology and a width of 18 contact poly pitches of 100 nm [52]. Accounting for technology scaling, the memristive implementation provides a 2X smaller footprint to [9] and a 3X smaller footprint to [10] adapted for comparable SNR. Comparing SNR at scaled voltages reveals another major advantage of implementing cascaded TDCIM using memristors.…”

“…For a binary network implementation with an energy efficiency of 1.05 POPS/W [9] devotes 22% of total MAC area to memory. In [10] a cascaded TDCIM for ternary operation at 716 TOPS/W is shown using custom current starved inverters combined with SRAM. The used custom SRAM integrates delay cell, leading to memory footprint of 50% of the total MAC area.…”

DATIC: A Data-Aware Time-Domain Computing-in-Memory-Based CNN Processor With Dynamic Channel Skipping and Mapping

“…Restricted by the voltage or current headroom, the magnitude of data and the number of MACs processed in CIMs are limited. However, time-domain CIMs (TD-CIMs) [9][10][11][12][13][14] represent data and compute MACs by delay signals including pulsewidth or path latency. Since delay signals have no circuital limitation like voltage headroom, the data magnitude and MAC count processed in TD-CIMs can be arbitrary large in principle.…”