2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) 2012
DOI: 10.1109/icassp.2012.6288490
|View full text |Cite
|
Sign up to set email alerts
|

Teaching and research in FPGA based Digital Signal Processing using Xilinx System Generator

Abstract: This paper presents an efficient approach for the implementation of typical DSP structures studied in class or conceived during research. This scheme is beneficial where the objective is to implement the physical working of complex DSP structures or algorithms without requiring detailed knowledge of hardware design and hardware description languages. The approach is based on the Xilinx System Generator for DSP tool, which integrates itself with the MATLAB based Simulink Graphics environment and relieves the us… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2

Citation Types

0
2
0

Year Published

2016
2016
2021
2021

Publication Types

Select...
3
2
1

Relationship

0
6

Authors

Journals

citations
Cited by 6 publications
(2 citation statements)
references
References 14 publications
0
2
0
Order By: Relevance
“…Thirdly, a system on chip (SoC), containing FPGA and processor cores on a single chip, can also be used for this purpose but it is again a costly solution and overkills the problem [12][13][14][15]. Fourthly, customized computational units can be designed in FPGA using hardware description language (HDL) [16][17]. Such units normally incorporate different IP cores and their HDL source code cannot be exported directly to other FPGAs, ASICs and integrated software environments (ISEs).…”
Section: Introductionmentioning
confidence: 99%
“…Thirdly, a system on chip (SoC), containing FPGA and processor cores on a single chip, can also be used for this purpose but it is again a costly solution and overkills the problem [12][13][14][15]. Fourthly, customized computational units can be designed in FPGA using hardware description language (HDL) [16][17]. Such units normally incorporate different IP cores and their HDL source code cannot be exported directly to other FPGAs, ASICs and integrated software environments (ISEs).…”
Section: Introductionmentioning
confidence: 99%
“…It is compatible with MATLAB Simulink. There is large amount of Digital Signal Processing (DSP) blocks available which includes FIR compilers, multipliers, adders, delays, and many more [ 12 ]. Black box is used for manual Verilog coding; it provides maximum flexibility but can be complex for some designs.…”
Section: Introductionmentioning
confidence: 99%