Technique for Large Elevation of Source/Drain Using Implantation Mediated Selective Etching

Abstract

A process involving implantation mediated selective etching has been developed for source/drain elevation of metal-oxidesemiconductor devices. A 100 nm thick epitaxial silicon/polysilicon layer was formed on a patterned Si/SiO 2 structure by chemical vapor deposition ͑CVD͒ at 700°C. Samples were then implanted with 2 ϫ 10 14 /cm 2 argon at 140 keV in the ͗100͘ channeling direction, followed by 1 min annealing at 420°C. The polysilicon layer was then removed by wet etching with more than an order of magnitude selectivity over epitaxial silicon. The resulting structure of elevated silicon is free from faceting effects. The process is independent of sidewall/isolation materials, and not bound by thickness limits.Selective elevation of silicon on patterned structures has been studied for a long time. 1 The prospective application is on elevated source/drain ͑ESD͒ structures in ultralarge scale integration ͑ULSI͒ technology. 2 ESD regions in complementary metal-oxidesemiconductor ͑CMOS͒ devices provide the extra silicon thickness that allows the formation of silicide contacts for very shallow junctions. Selective epitaxial growth ͑SEG͒ by chemical vapor deposition ͑CVD͒ is commonly being used in ESD formation. 2-5 However, the thickness of silicon layers formed by SEG is limited by the onset of polysilicon nucleation on insulating layers. Variation of SEG-Si thickness over the surface has also been reported. 3,4 But, most important, there is a natural tendency of forming ͑111͒ and ͑311͒ facets along pattern edges during the SEG growth. 5 These facets result in thin or almost negligible elevation of source/drain region near the gate sidewall. This seems to be a bottleneck in the SEG technique as the source/drain metallization, and also the junction tends to be deeper along the gate sidewall, causing additional leakage and short channel effects, respectively. 6 Careful processing of the material and optimization of growth conditions have been used for facet-free epitaxy, but only up to a thickness of 80 nm. 7 In this paper, we report on an approach for elevation of source/drain without thickness limits or faceting problems. 100 nm thick selective elevation of silicon has been achieved on a Si/SiO 2 patterned structure. The process involves conventional nonselective CVD growth, followed by an implantation mediated selective etching. ExperimentalA 220 nm thick oxide was formed on silicon ͑001͒ by dry oxidation at 1100°C. Samples were then patterned along the ͗100͘ direction using standard lithography and reactive ion etching ͑RIE͒. Low pressure chemical vapor deposition ͑LPCVD͒ was done on the patterned samples at 700°C using a SiH 4 /H 2 gas flow. The CVD grown samples were implanted with argon at 140 or 200 keV with doses of 2 ϫ 10 14 or 4 ϫ 10 14 /cm 2 . The implantation was oriented along the ͗100͘ channeling direction. Implanted samples were annealed for 1 min at 420 or 500°C. A solution of HF:HNO 3 :CH 3 COOH ͑1:80:120͒ was used for wet etching. Etching depths were measured in a Sloan Dektak 3030 surface profile mea...

Self-Aligned Planar Double-Gate Field-Effect Transistors Fabricated by a Source/Drain First Process

“…A thick selective elevation of 100 nm is performed by implantation mediated selective etching. 24) The BG surface is roughened after the selective etching. A succeeding high-temperature treatment, 850 C for 5 min in an ultrahigh vacuum, smoothes out the BG surface ready for the forthcoming channel deposition.…”