Technology CAD of silicided Schottky barrier MOSFET for elevated source–drain engineering

Saha, Anirban; Chattopadhyay, Sanatan; Bose, Chayanika; Maiti, C. K.

doi:10.1016/j.mseb.2005.08.098

Cited by 3 publications

(4 citation statements)

References 17 publications

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“…In process simulation, the result of an implantation step is mostly described by a so-called pearson function where as the diffusion equation is solved to derive the influence of an annealing step. The process steps are taken from Table1 and from reference paper [3,4].The initial grid has to be defined before any further steps of the design. A fine grid exist to those area of simulation structure where ion implantation will occur, where p-n junction will be formed.…”

Section: Process Simulationmentioning

confidence: 99%

“…The performance investigation is done in terms of trans-conductance (g m ), output conductance (g ds ), voltage gain (A v ), transistor cutoff frequency(f T ) and maximum frequency of oscillation (f max ) [3,7], and also a comparison is made for an engineered device with a non-engineered device of same channel length. The extraction of Y and h parameter is done from the simulation result for g m , g ds , and frequency response of Si n-MOSFET.…”

Section: Ivperformance Investigationmentioning

confidence: 99%

“…According to ITRS roadmap [2],a precisely controlled process flow for the incorporation of new materials in Si CMOS technology is crucial for nanoscale devices. Also,an increased functionality at low cost leads an excessive high packaging density for VLSI chips, leads to an aggressive scaling of MOSFETs [3].…”

Section: Introductionmentioning

confidence: 99%

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Virtual Fabrication and Analog Performance of Sub-40nm Bulk MOSFET Using TCAD TOOL

Amin¹,

Alam²

2011

IJCSI

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Virtual Fabrication of sub-40nm Bulk MOSFET is carried out under channel engineering and source drain engineering process. These structures enable more aggressive device scaling in nano-scale region because of their ability to control short channel effects. How ever during scaling the junction depth should also be scaled down, which increases parasitic resistance so silicidation technique has been applied to reduce their effects on device. Analog performance has been measured in terms of gm, gds ,Av ,fT and fmax .The simulation result predict that gm is 3.75ms for engineered MOSFET as compared to nonengineered MOSFET with gm of 2.9ms for similar gate length, similarly Av for engineered device is 17.5db and for non-engineered device is 6.96db,fT is 146GHz and for non-engineered fT is 65GHz,fmax is 299GHz for engineered device and for nonengineered device fmaxis 170GHz and a comparison of an engineered device is done with a non engineered device to investigate the improved performance of an engineered device as compared to a non engineered device. Silvaco TCAD Tool is used for Virtual fabrication and simulation. ATHENA process simulator is used for virtual fabrication and ATLAS device simulator is used for device characterization.

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Section: Process Simulationmentioning

confidence: 99%

Section: Ivperformance Investigationmentioning

confidence: 99%

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Virtual Fabrication and Analog Performance of Sub-40nm Bulk MOSFET Using TCAD TOOL

Amin¹,

Alam²

2011

IJCSI

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“…Schottky-barrier MOSFET (SB-MOSFET) offers an alternative device technology to minimize parasitic S/D resistances and eliminate the need for ultra-shallow junctions [1][2][3][4][5][6][7][8][9]. The characteristics of nano scale SB-MOSFETs based on ballistic simulation and constant effective mass approximation have been reported [10,11].…”

Section: Introductionmentioning

confidence: 99%

High frequency performance of nano-scale ultra-thin-body Schottky-barrier n-MOSFETs

Liu

Han

2011

Sci. China Inf. Sci.

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The high frequency performances of nano-scale ultra-thin-body (UTB) Schottky-barrier nMOSFETs (SB-nMOSFETs) are investigated using 2D full-band self-consistent ensemble Monte Carlo method. The UTB SB-nMOSFET devices offer excellent RF performance with high values of f T and fmax. The significant dependence of f T and fmax on gate voltage and weak dependence on barrier height are demonstrated. Meanwhile, the significant dependence of gm and g ds on both gate voltage and SB height are shown. Moreover, the scalability of f T is outstanding and close to the ideal case (f T ∝ 1/L 2 g ). The high frequency performances of 45 nm channel length SB-nMOSFETs at ballistic transport limit are also investigated. Results show that scattering strongly affects the capacitances Cgs, C gd and C ds . At ballistic transport limit the f T and fmax are almost 10 times larger. The Scattering effects in nano-scale SB-nMOSFETs cannot be neglected.Keywords Monte Carlo, ultra thin body (UTB), Schottky-barrier MOSFETs (SB-MOSFETs), high frequency CitationDu G, Liu X Y, Han R Q. High frequency performance of nano-scale ultra-thin-body Schottky-barrier n-MOSFETs.

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RF dynamic and noise performance of Metallic Source/Drain SOI n-MOSFETs

Martı́n

Pascual

Rengel

2012

Solid-State Electronics

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Technology CAD of silicided Schottky barrier MOSFET for elevated source–drain engineering

Cited by 3 publications

References 17 publications

Virtual Fabrication and Analog Performance of Sub-40nm Bulk MOSFET Using TCAD TOOL

Virtual Fabrication and Analog Performance of Sub-40nm Bulk MOSFET Using TCAD TOOL

High frequency performance of nano-scale ultra-thin-body Schottky-barrier n-MOSFETs

RF dynamic and noise performance of Metallic Source/Drain SOI n-MOSFETs

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