Technology for the formation of refractory metals for micro- and nanoelectronics products

Abstract

Metal silicides play a significant role in the preparation of ohmic contacts and Schottky barriers on silicon. The formation of ohmic contacts is carried out by applying a metal film with a thickness of ∼ 100 nm to silicon, followed by annealing at temperatures of 400–600 °C, as a result of which there is a reaction between silicon and metal with the formation of silicide. With this technology, silicon diffusion leads to instability of devices. In this regard, the authors developed an improved technology for the formation of silicides of refractory metals to obtain ohmic contacts. Ion implantation allows, due to ionic mixing, forming nickel silicide on the surface of the samples when heated. It is important that, with an increase in the radiation dose, the formation of Ni2Si silicide slows down. This effect can be explained by the formation of a dielectric Ni3Si2. Similar phenomena were observed during the bombardment by oxygen and nitrogen ions.

Development of Schottky barrier field-effect transistors (SB-MOSFET) with ultra-low thermal budget

“…However, these fast transistors require rather complex processing steps with high thermal budgets, complex device architectures or even the introduction of additional terminals aimed to better control charge transport phenomena at the cost of increasing total power consumption [5][6][7], just like the additional 'Schottky bias' terminal in a MOSFET able to reach a subthreshold slope of 6 mV/dec [8]. Nevertheless, compared to conventional planar MOSFETs, more advantages in Schottky-barrier MOSFET devices like the low parasitic S/D resistance, low-temperature processing for S/D formation, elimination of parasitic bipolar action, inherent physical scalability to sub 10 nm gate length dimensions (due to the low resistance of the metal and the atomically abrupt junctions formed at a metal/silicon interface) [9], the choice of refractory metals for increased resistance to atomic diffusion trough the passivation layer and into the silicon substrate [10], etc, highlight the potential of a simple device able to show high performance with a low-cost and CMOS-compatible process. Moreover, a proper control on the Schottkybarrier height (SBH) of metal/semiconductor interfaces, could lead to applying well controlled Schottky-barrier contacts in advanced electron devices like the atomristor and other devices based on 2D materials [11,12].…”

Low temperature passivation of silicon surfaces for enhanced performance of Schottky-barrier MOSFET

“…Even though there have been immediate solutions to minimize Fermi level pinning at metal/semiconductor interfaces (mainly by the introduction of ultra-thin high-dielectric constant metal oxides [27]), these solutions complicate the transistor processing while increasing its total thermal budget, thus preventing introduction of these devices in advanced BEOL stages of an integrated circuit [27]. Nevertheless, compared to conventional planar MOSFETs, more advantages in Schottky-barrier MOSFET devices like the low parasitic S/D resistance, low-temperature processing for S/D formation, elimination of parasitic bipolar action, inherent physical scalability to sub 10 nm gate length dimensions (due to the low resistance of the metal and the atomically abrupt junctions formed at a metal/silicon interface) [28], the choice of refractory metals for increased resistance to atomic diffusion trough the passivation layer and into the silicon substrate [29], etc, highlight the potential of a simple device able to show high performance with a low-cost and CMOS-compatible process.…”