Technology, performance, and computer-aided design of three-dimensional integrated circuits

Das, Shamik; Fan, Andy; Chen, Kuan‐Neng; Tan, Chuan Seng; Checka, Nisha; Reif, R.

doi:10.1145/981066.981091

Cited by 120 publications

(66 citation statements)

References 18 publications

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“…The network based communication infrastructures and three-dimensional (3-D) designs offer low power and high speed where multiple device layers are stacked together. The emergence of 3-D circuits provides an opportunity to reduce the wire length of global interconnects, resulting in an increase in performance and decrease in the power consumption [4,6]. The 3-D architecture reduces wiring length by a factor of √ , where is the number of layers used in NoC [8].…”

Section: Related Workmentioning

confidence: 99%

Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip

Khan

Ansari

2012

Open Computer Science

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Abstract:The Network-on-Chip (NoC) is an emerging communication technique for System-on-Chip (SoC) communications. The NoC uses multiple processors, usually targeted for embedded applications and other applications [3,13]. Performance of the bus is degraded by the increasing number of processing elements and transaction oriented model [13]. This has attracted much attention for applying wireless network protocols as CDMA, TDMA, and dTDMA in SoC. The TDMA systems use a fixed number of timeslots. This protocol wastes bandwidth when some timeslots are allocated but not used. The dynamic TDMA (dTDMA) bus arbiter dynamically grows and shrinks the number of timeslots to match the number of active transmitters [14]. In this paper, we present a design of area-efficient switch for inter-layer communications in 3-D NoC. The arbitration logic in the switch is based on a programmable priority encoder. A 640-bit message with uniform random destination data pattern was injected per IP per machine clock cycle. We have obtained the maximum clock frequency of 2.09 GHz for 96(4 x 8 x 3) IP cores connected in a mesh topology. The presented architecture demonstrates their superior functionality in terms of speed, latency, area, and power consumption as compared with the existing implementation [14]. The maximum power consumption of the proposed area-efficient programmable arbiter is 0.625 mW. The design is synthesized using 180nm TSMC Technology.

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Section: Related Workmentioning

confidence: 99%

Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip

Khan

Ansari

2012

Open Computer Science

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“…Though TSVs are wider than typical metal wires, TSVs have very short height, since each wafer is thinned to only tens of microns. After fabrication, each wafer is thinned to only 10-100 µm in thickness [3,14], and then TSVs that have pitches of only 4-10 µm 0 are etched through a bulk silicon. Lastly, thermo-compression is used to bond individual layers together to form the 3D integration structure [27].…”

Section: Related Workmentioning

confidence: 99%

Quantifying Architectural Impact of Liquid Cooling for 3D Multi-Core Processors

Jang¹,

Yoon²,

Kim³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-For future multi-core processors, 3D integration is regarded as one of the most promising techniques since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Conventional air cooling schemes are not enough for 3D multi-core processors due to the limit of the heat dissipation capability. Without more efficient cooling methods such as liquid cooling, the performance of 3D multi-core processors should be degraded by dynamic thermal management. In this paper, we examine the architectural impact of cooling methods on the 3D multi-core processor to find potential benefits of liquid cooling. We first investigate the thermal behavior and compare the performance of two different cooling schemes. We also evaluate the leakage power consumption and lifetime reliability depending on the temperature in the 3D multi-core processor.

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“…State-of-the-art 3D integration employs thin dies that results in d2d via lengths from 5 µm to 20 µm [9]. Assuming a d2d via length of 10 µm, the worst-case capacitance of a d2d via surrounded by 8 other vias is computed as 0.594e-15 F/µm.…”

Section: Interconnect Evaluationmentioning

confidence: 99%

“…The total power consumed by all 1409 vias adds up to only 15.49 mW. State-of-the-art width of each via is 5 µm [9]. The area overhead for all the vias is 0.07 mm 2 assuming that the width and spacing between each via is 5 µm.…”

Section: Interconnect Evaluationmentioning

confidence: 99%