Technology review and assessment of nanoimprint lithography for semiconductor and patterned media manufacturing

Abstract

The semiconductor and hard disk drive industries are investigating nanoimprint for future high volume manufacturing of memory devices and patterned media. Nanoimprint, a form of 1× contact lithography, is one of the few technologies capable of meeting the resolution requirements for next generation electronic and storage devices. Its ability to produce small features with low line width roughness and critical dimension uniformity has been demonstrated by multiple sources. Significant improvements in defectivity have been shown; overlay has improved to within a factor of 2 of that required by the International Technology Roadmap for Semiconductors for 22 nm node flash memory devices; and next generation tools, templates, and processes are being commercialized and tested at end-user sites. Defectivity, throughput, and infrastructure remain as critical challenges, but each has experienced marked improvements in the past year. This technology review and assessment covers critical aspects of nanoimprint for both semiconductor and patterned media manufacturing. It focuses on jet and flash imprint lithography, the type of nanoimprint most often considered for these two applications. The requirements and current status of nanoimprint with respect to high volume manufacturing are presented, and critical aspects are discussed. C 2011 Society of PhotoOptical Instrumentation Engineers (SPIE).

Nanomanufacturing: A Perspective

“…the 2× nm nodes). 87,88,89,90 Another potential benefit comes from the ability of nanoimprint to print multiple pattern levels simultaneously, which can result in a significant reduction in the number of process steps needed to complete a device. 91,92,93,94,95 Aside from meeting overlay requirements, the principal obstacle facing the technology is for it to achieve the same throughput and low level of defects 96 as photolithography.…”

“…109,110 A less demanding specification for defect density translates into a reduced need for costly defect inspection during manufacturing. As the technology evolves and defect levels decrease, it is even being considered for the production of flash memory, which has relatively relaxed overlay requirements, 89,111 though defect levels will need to be reduced to ~ 0.1 cm −2 . 112 …”

Electrochemical Surface Processes and Opportunities for Material Synthesis

“…Electrodeposition is ideal for this purpose, since its selectivity enables growth only at conductive locations, which could be predetermined by a suitable pattern; in addition, the process would be completely additive, avoiding the etching processes necessary when using physical deposition methods, which necessarily damage the magnetic islands and affect their magnetization switching processes. Potential patterning methods that are currently being investigated include electron beam lithography, a slow, serial process, and nanoimprint lithography, which consists in the replication of a quartz mold by a suitable mold, which is then used to imprint a resist spun onto the disk [146].…”

Enhanced patterning by tilted ion implantation

“…Extreme ultraviolet (EUV) lithography, nanoimprint lithography (NIL) and directed self-assembly (DSA) of block copolymers (BCP) are techniques that have been extensively investigated as candidates for next-generation lithography [5][6][7][8][9][10][11]. However, technical challenges remain for their practical application: the development of a high-power light source (needed for high exposure throughput) for EUV lithography [5][6][7][8]; the need for high-resolution template patterning and defect control for NIL [9]; the need for defect control, lack of design flexibility, and low throughput of DSA [10,11]. Therefore, there remains an urgent need to develop more cost-effective approaches for scaling down the minimum feature size and increasing the density of features in an integrated circuit "chip," to sustain Moore's Law.…”