TEI-Turbo: temperature effect inversion-aware turbo boost for finfet-based multi-core systems

Cai, Ermao; Marculescu, Diana

doi:10.1109/iccad.2015.7372611

Cited by 20 publications

(13 citation statements)

References 26 publications

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“…The previous research on TEI-aware techniques exploited TEI to perform voltage scaling for dynamic thermal management in simple VLSI circuits [19], and to frequency upscaling as a turbo mode in a multicore processor [20]. Applying both works directly to NoCs is not prudent, because NoCs are fundamentally different from those simple circuits or multicore processors.…”

Section: Tei-noc Methodologymentioning

confidence: 99%

“…The delay of bulk CMOS logic gates operating at super-threshold V dd increases as the temperature rises, which eventually lower the circuit speed. That is why the commercial standard cell libraries targeting nominal voltage operation typically have the worst-case timing corner at the highest temperature, e.g., 125°C [19], [20].…”

Section: Ulp Noc Characteristics a Temperature Effect Inversion mentioning

confidence: 99%

“…From the figure, we can clearly observe the TEI phenomenon. Due to the TEI phenomenon, the worst-case timing corner of ULP circuits occurs at the lowest operating temperature of the circuits, e.g., -25°C [17], [20]. Intuitively, this consequence gives rise to a new policy for voltage and/or frequency scaling at elevated chip temperatures.…”

Section: Ulp Noc Characteristics a Temperature Effect Inversion mentioning

confidence: 99%

“…This effect is called temperature effect inversion (TEI) [19]. Recent studies have conducted on exploiting this TEI phenomenon to perform dynamic power and thermal management by using voltage scaling [19] and frequency scaling [20]. The present paper, which is motivated by the TEI phenomenon in ULP circuits, presents a power management algorithm for ULP NoCs.…”

Section: Introductionmentioning

confidence: 99%

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TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion

Han

Lee

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern of system-on-chip designers. Ultra-low power (ULP) VLSI circuits have been receiving considerable interest from both academia and industry as the best-suited techniques for IoT devices, which can take full advantage of power-saving that voltage scaling potentially achieves. Consequently, research on ULP designs has begun to yield tangible outcomes, namely ULP circuits. However, little attention has been paid to ULP Networkon-Chip (NoC), although the NoC is an essential of the ULP chips, and its power consumption accounts for a significant portion of the total power. This paper focuses on ULP NoCs, and presents a new power management method that exploits delay vs. temperature characteristics of ULP circuits. Recent studies on ULP circuits show that delay vs. temperature characteristics are fundamentally different from normal circuits, i.e., the delay of the ULP circuits implemented in state-of-the-art bulk CMOS operating at low supply voltages or in FinFET technologies decreases with increasing temperature, a phenomenon known as the temperature effect inversion (TEI). Starting with an intuition that at a certain temperature point, power savings without performance penalty can be achieved by increasing the router frequency to create the opportunity to turn off some routers in ULP NoCs, or by decreasing the NoC supply voltage level, an optimization method is presented to maximize the power savings with minor performance penalty. To validate the proposed method, a concrete ULP NoC simulator (TEI-Noxim) has been developed. Experimental results demonstrate that TEI-aware NoC achieves an average of 36.0% power reduction over 21 applications.

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Section: Tei-noc Methodologymentioning

confidence: 99%

Section: Ulp Noc Characteristics a Temperature Effect Inversion mentioning

confidence: 99%

Section: Ulp Noc Characteristics a Temperature Effect Inversion mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion

Han

Lee

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…The benefits of TEI can be maximized with the assist of novel power management techniques that can dynamically tune the voltage or frequency based on the real-time temperature 43 or novel algorithms that can determine the maximum performance under power constraints. 44 Since thermal issues also emerge as important reliability concerns throughout the system lifetime, the TEI effect can compensate some of the performance degradation introduced by reliability threats such as BTI and EM. 42,45 The optimal operating temperature can be exploited to reduce design cost and runtime operating power for overall cooling with the proper utilization of the TEI effect.…”

Section: Thermal Effect Inversion (Tei)mentioning

confidence: 99%

Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

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It has been almost a decade since FinFET devices were introduced to full production; they allowed scaling below 20 nm, thus helping to extend Moore's law by a precious decade with another decade likely in the future when scaling to 5 nm and below. Due to superior electrical parameters and unique structure, these 3-D transistors offer significant performance improvements and power reduction compared to planar CMOS devices. As we are entering into the sub-10 nm era, FinFETs have become dominant in most of the high-end products; as the transition from planar to FinFET technologies is still ongoing, it is important for digital circuit designers to understand the challenges and opportunities brought in by the new technology characteristics. In this paper, we study these aspects from the device to the circuit level, and we make detailed comparisons across multiple technology nodes ranging from conventional bulk to advanced planar technology nodes such as Fully Depleted Silicon-on-Insulator (FDSOI), to FinFETs. In the simulations we used both state-of-art industry-standard models for current nodes, and also predictive models for future nodes. Our study shows that besides the performance and power benefits, FinFET devices show significant reduction of short-channel effects and extremely low leakage, and many of the electrical characteristics are close to ideal as in old long-channel technology nodes; FinFETs seem to have put scaling back on track! However, the combination of the new device structures, double/multi-patterning, many more complex rules, and unique thermal/reliability behaviors are creating new technical challenges. Moving forward, FinFETs still offer a bright future and are an indispensable technology for a wide range of applications from high-end performance-critical computing to energy-constraint mobile applications and smart Internet-of-Things (IoT) devices.

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Design and Aging Challenges in FinFET Circuits and Internet of Things (IoT) Applications

Guo

Stan

2019

Circadian Rhythms for Future Resilient Electronic Systems

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TEI-Turbo: temperature effect inversion-aware turbo boost for finfet-based multi-core systems

Cited by 20 publications

References 26 publications

TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion

TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion

Back to the Future: Digital Circuit Design in the FinFET Era

Design and Aging Challenges in FinFET Circuits and Internet of Things (IoT) Applications

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