Temperature-aware microarchitecture

Abstract

With cooling costs rising exponentially, designing cooling solutions for worst-case power dissipation is prohibitively expensive. Chips that can autonomously modify their execution and power-dissipation characteristics permit the use of lower-cost cooling solutions while still guaranteeing safe temperature regulation. Evaluating techniques for this dynamic thermal management (DTM), however, requires a thermal model that is practical for architectural studies.This paper describes HotSpot , an accurate yet fast and practical model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package. Validation was performed using finite-element simulation. The paper also introduces several effective methods for DTM: "temperature-tracking" frequency scaling, "migrating computation" to spare hardware units, and a "hybrid" policy that combines fetch gating with dynamic voltage scaling. The latter two achieve their performance advantage by exploiting instruction-level parallelism, showing the importance of microarchitecture research in helping control the growth of cooling costs.Modeling temperature at the microarchitecture level also shows that power metrics are poor predictors of temperature, that sensor imprecision has a substantial impact on the performance of DTM, and that the inclusion of lateral resistances for thermal diffusion is important for accuracy.

Thermal/performance trade-off in network-on-chip architectures

“…We conducted several experiments using a modified version of GEM5 as an appropriate cycle-accurate simulator (http: //gem5.org), a modified version of McPAT [17] and Orion [13] detailed models for cores and routers power consumption estimates, and the widely used HotSpot thermal model [24] to generate chip temperature map. The reference architecture we target is an Alpha21364 network architecture [20], that is used in real Web-servers and Data-centre contexts; commercial examples exist for this kind of architecture, based on the Alpha21264 processor core.…”

“…A topological ring is associated with a set of cores in the architecture, and rings are placed concentric each other. Each core belongs to one and only one ring, and cores belonging to the same ring share similar temperature dissipation properties: for instance, all the cores belonging to the outermost topological ring are placed against the chip edge, with direct impact on the way heat is dissipated and temperature is exchanged with package and ambient [24].…”

Compact thermal modeling for packaged microprocessor design with practical power maps

“…Thermal management and related design problems continue to be identified by the Semiconductor Industries Association Roadmap [5] as one of the five key challenges during the next decade to achieve the projected performance goals of the industry. Thus, accurate and efficient thermal modeling and analysis is vital for the thermal-aware chip and package designs to improve performance, reliability, as well as for efficient online temperature regulation and management [6][7][8].…”

“…Existing work on HotSpot [19,8] attempts to solve this problem by generating the compact thermal model in a bottom-up manner based on processor and package structures. However, such whitebox models may suffer from accuracy issues for complicated structures and boundary conditions, which are not properly modeled in the starting models.…”

Temperature aware task sequencing and voltage scaling

“…A 10 − 15 o C reduction in peak temperature can result in 2X increase in the lifetime of the chip [2]. Carrier mobility decreases with increase in temperature; thus higher operating temperatures can result in more frequent transient errors [19]. Leakage current increases exponentially with increasing temperature and the positive feedback between leakage power and temperature can result in a thermal runaway.…”