Temperature-aware task scheduling algorithm for soft real-time multi-core systems

Wu, Guowei; Xu, Zichuan

doi:10.1016/j.jss.2010.08.017

Cited by 12 publications

(1 citation statement)

References 26 publications

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“…Another example for task scheduling and DVFS for energy and temperature management is discussed in [87] for heterogeneous MPSoCs. DTM methods for multi-core systems which include task/thread scheduling and task migration are discussed in [88,89,90]. Temperature is also regulated by managing task workloads, i.e.…”

Section: Prevalent Power Thermal and Fault Management Methodsmentioning

confidence: 99%

A Decision-Making Method for Run-Time Structural Adaptation Of FPGA-Based SOCS to Variations in Workload, Power Budget, Die Temperature, and Hardware Resources

Sharma

2024

Preprint

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<p>Embedded systems for application domains like robotics, aerospace, defense, etc. nowadays are developed on System-on-Chip (SoC) platforms based on Field Programmable Gate Array (FPGA) devices to support computation-intensive multi-task multi-modal dynamic workloads common for these applications. These systems therefore face the challenge to sustain the performance of their dynamic workloads in presence of variations in power budget, die temperature, and/or occurrence of hardware faults. This work proposes Run-time Structural Adaptation (RTSA) as a mechanism for mitigating these factors. One of the major contributions of this work is creation of a run-time decision-making method, ‚ÄúExplorer‚Äù, to carry out RTSA for FPGA-based SoCs and mitigate variations in the internal and external factors simultaneously. Whenever there is a change in the system‚Äôs set of constraints, Explorer selects an appropriate variant of hardware processing circuit for each active task from a large design space to form a system conÔ¨Åguration that satisÔ¨Åes each task‚Äôs performance speciÔ¨Åcation and all other system constraints. To support the practical deployment of Explorer, this work presents a method to derive run-time power consumption and die temperature estimation models for any FPGA-based device. This novel methodology of model derivation based on the FPGA platform and application running on it is another contribution of this work. The model derivation methods are formulated after detailed experimental analysis of power consumption and thermal behaviors of recent FPGA devices. Explorer can evaluate potential system conÔ¨Ågurations using the derived models to select a suitable system conÔ¨Åguration for RTSA. Experimental implementation of Explorer on the Zynq XC7Z020 SoC shows worst case execution time of 130 us, which demonstrates its suitability for RTSA for most applications associated with multi-stream computation-intensive tasks. This work also proposes an approach for automating model derivation which helps systems self-derive their model coefficients during system production and re-derive them due to changes in system platform, application, and/or environmental conditions. This significantly reduces model derivation time while avoiding any human involvement. This work thus presents the methods and models necessary to enable real systems utilizing FPGA devices to carry out RTSA and sustain their dynamic workloads amid dynamic environmental and hardware resource constraints.</p>

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