2018
DOI: 10.1587/elex.15.20180878
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Temperature-dependent characterizations on parasitic capacitance of tapered through silicon via (T-TSV)

Abstract: With increasing integration density of three-dimensional ICs, temperature is one of the major concern of circuit design, which influences the performance and reliability. In this paper, the parasitic capacitance of tapered TSV (T-TSV) with respect of thermal properties is studied. The concept of the Temperature Coefficient of Capacitance (TCC) is proposed to model the sensitive of TSV capacitance to temperature. It is found that TSV capacitance is sensitive to temperature under high frequency application, and … Show more

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Cited by 3 publications
(2 citation statements)
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“…Nevertheless, the external factors are not discussed due to the integration of dielectric materials. The effect of temperature is examined on the parasitic capacitance of the tapered through silicon [18]. The impact of relative humidity is investigated on surface mount solid tantalum capacitors [19].…”
Section: Introductionmentioning
confidence: 99%
“…Nevertheless, the external factors are not discussed due to the integration of dielectric materials. The effect of temperature is examined on the parasitic capacitance of the tapered through silicon [18]. The impact of relative humidity is investigated on surface mount solid tantalum capacitors [19].…”
Section: Introductionmentioning
confidence: 99%
“…TSV provides low loss vertical electrical connection, so it has been widely studied in recent years [7][8][9][10][11]. and it has the advantages of lower loss, smaller size, integrability and good transmission characteristics [12][13][14][15][16][17][18], which makes it not only was used as a vertical interconnect in 3D-IC, but also widely used in the passive device manufacturing [19][20][21][22][23]. In this paper, a miniature TSV based branch line coupler for S-band is proposed.…”
Section: Introductionmentioning
confidence: 99%