Temperature dependent study of Fin-FET drain current through optimization of controlling gate parameters and dielectric material

Das, Rinku Rani; Maity, Santanu; Muchahary, Deboraj; Bhunia, Chandan Tilak

doi:10.1016/j.spmi.2017.01.041

Cited by 20 publications

(5 citation statements)

References 8 publications

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“…6b, for ΔT = 100 K, 12% degradation of SS is observed for GNRFET with L G = 10 nm, compared to 48% degradation reported for Si FinFET with L G = 15 nm. 40 The V T variation with temperature in GNRFET is 0.41 mV/°C, against ∼0.9 mV/°C for Si FinFET. 41 In parallel, gate delay and PDP is also reduced by a margin of ∼13% and ∼15% respectively, for ΔT = 100 K, regardless of L G due to increase in both Q off and I on , as shown in Figs.…”

Section: Resultsmentioning

confidence: 93%

Influence of Device Parameters on Performance of Ultra-Scaled Graphene Nanoribbon Field Effect Transistor

Hasan

Nishat

Hossain

et al. 2020

ECS J. Solid State Sci. Technol.

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Recent advances in graphene nanoribbon (GNR) field-effect transistors (FETs), with finite band-gap, have shown great promise for their use in ultra-scaled, low power and high speed device applications. Here, we use quantum mechanical simulations, based on non-equilibrium Green’s function (NEGF), to study the electrical characteristics of a sub-10 nm gate length GNRFET with double gate structure. Tight-binding approximation is used to extract the energy bands of GNR and the results are validated with density functional theory (DFT) calculations. Key electrical parameters are computed for different dielectric material, source/drain doping and temperature combining the channel length scaling beyond 10 nm to study performance variation. Results reveal that change in source/drain doping shows significant impact on performance for shorter channel, while the opposite tendency is observed for dielectric constant (k) variation. GNRFET showed robustness against temperature variation compared to conventional Si devices. Finally, the results were benchmarked against the performance metrics of high performance and low power CMOS devices in the 5-nm technology node. A significant rise in leakage current beyond the LP requirement was observed for gate lengths below 5 nm. Results obtained from this study can provide useful insights in the design and implementation of next generation GNRFETs.

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Section: Resultsmentioning

confidence: 93%

Influence of Device Parameters on Performance of Ultra-Scaled Graphene Nanoribbon Field Effect Transistor

Hasan

Nishat

Hossain

et al. 2020

ECS J. Solid State Sci. Technol.

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“…The changes of sub‐threshold swing (SS) and V th with respect to temperature ( T ) are outlined in Figure 3g. Dependence of sub‐threshold swing and V th 33 on temperature can be determined by

SS goodbreak= \frac{60 T}{300},

V_{th} goodbreak= V_{oth} goodbreak- χ ((), T goodbreak- T_{0}),

where V oth is the threshold voltage at T = T 0 and χ is the temperature coefficient. The SS value increases with an increase in T that degrades the performance.…”

Section: Resultsmentioning

confidence: 99%

“…Das et al reported 32 the gate overlap to drain and source of FinFET reduce the leakage current and improve drain characteristics with a minimized value of SCEs. Reference [33] studied and explored the impact of the temperature variation of FinFET to analyze the short channel effect and observed that the device is more immune at low temperature. Kalyan et al 34 studied the variation of fin shape of junctionless accumulation mode bulk FinFET to analyze the analog/RF performance.…”

Section: Introductionmentioning

confidence: 99%

Impact of temperature on radio frequency/linearity and harmonic distortion characteristics of Ge multi‐channel fin shaped field‐effect transistor

Das

Maity

Chowdhury

et al. 2021

Int J RF Mic Comp-Aid Eng

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This dissertation demonstrates the reliability issues associated with the temperature of Ge multi‐channel fin shaped field‐effect transistor (Mch‐FinFET). Temperature dependence on short channel effectss such as threshold voltage (Vth), sub‐threshold swing (SS), and switching ratio are observed. The variation in temperature on various important radio frequency (RE)/analog, linearity, and harmonic distortion characteristics are studied and analyzed over a wide range of temperatures (300–500 K). The simulation study revealed that Mch‐FinFET devices exhibit 61.6% improvement in ION with minimum SS value. The improvement of SS, switching ratio and Vth can be observed with temperature fall. The enhancement in performance of various RF/analog attributes such transconductance, device efficiency, transconductance frequency product, gain frequency product, cut‐off frequency, and intrinsic gain with lowering of temperature. However, Mch‐FinFET device provides a significant improvement of higher‐order current and voltage intercept points such as IIP3, VIP2, VIP3, and 1 dB compression point with lesser harmonic distortion such as HD2, HD3, and THD at elevated temperature. The superior efficiency of DC and RF/analog attributes, greater linearity, and minor harmonic distortion performance of Mch‐FinFET make it more considerable to design low power Complementary metal–oxide–semiconductor (CMOS) circuits.

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“…Rinku et al [69] have studied the significance of temperature in FinFET to observe the SCEs parameter performances. The importance of gate length and dielectric materials is also studied.…”

Section: Non-ideal Effects On Finfetmentioning

confidence: 99%

FinFET to GAA MBCFET: A Review and Insights

Das,

Rajalekshmi,

James

2024

IEEE Access

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This review article presents a journey from Fin-shaped field effect transistor (FinFET) to gate-all-around multi-bridge channel field effect transistor (GAA MBCFET) technology, unraveling the evolution of semiconductor architectures. This article provides a concise yet insightful overview of the development of FinFET, exploring modified architectures, current trends, and associated constraints. The growing importance of other semiconductor materials instead of Si in FinFET or other technologies has been studied in detail. The article explores an emerging technology called 'GAA MBCFET', highlighting its advantages over FinFET. It also delves into the notable drawbacks and complex fabrication challenges associated with the upcoming GAA MBCFET technology. INDEX TERMS Gate-All-Around (GAA), Multi-Bridge Channel (MBC), Silicon on Insulator (SOI)

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Temperature dependent study of Fin-FET drain current through optimization of controlling gate parameters and dielectric material

Cited by 20 publications

References 8 publications

Influence of Device Parameters on Performance of Ultra-Scaled Graphene Nanoribbon Field Effect Transistor

Influence of Device Parameters on Performance of Ultra-Scaled Graphene Nanoribbon Field Effect Transistor

Impact of temperature on radio frequency/linearity and harmonic distortion characteristics of Ge multi‐channel fin shaped field‐effect transistor

FinFET to GAA MBCFET: A Review and Insights

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