Temperature effect on the heavy-ion induced Single-Event Transients propagation on a CMOS Bulk 0.18 µm inverters chain

Abstract

The ATLAS simulation tool from SILVACO is used for 3D simulations. This software solves the transient semiconductor device equations in three dimensions, including the Poisson equation and the current continuity equations. The technology modeled in this work is a CMOS Bulk 0.18 urn process manufactured by ATMEL and transistors are designed for 1.8 V operation bias. The 3D inverter is modeled on a p-type silicon substrate. The doping profiles have been obtained by process simulation with ATHENA in order to obtain a realistic inverter device. The 3D structure is in agreement with the layout dimensions of this technology as shown on Fig. 1. The size of the NMOS and PMOS transistor,W/L, is respectively 1.4 and 2. For all simulations, the following models were used: Fermi-Dirac statistics, bandgap narrowing effect (BGN), Shockley-ReadHall (SRH) and Auger recombination, impact ionization, and the Lombardi mobility [11] which takes into account the mobility variation with the normal and parallel electric field, doping concentration and temperature. In ATLAS, the magnitude decreases. Thus, one can presume that the wide temperature range of a spatial environment (from 218 to 418 K) can modify the shape of the SETs. In this paper, device simulations are performed at 218,300 and 418 K on a CMOS Bulk 0.18 urn inverter from ATMEL. We investigate the variations of the heavy-ions induced SETs for various impact locations at the three considered temperatures. This paper focuses on the voltage pulse width because its value is often used as a critical parameter in designing SET-mitigation circuits [2]. In the part II of the paper, the 3D modeled device and the simulation conditions are described. The part III shows the influence of the temperature on the SET pulse for a track crossing the off-NMOS drain (i.e. the sensitive region) and for a track striking the device far from this sensitive region. In the part IV, we complete the investigation with Spice simulations in order to define the implication of the temperature on the SETs propagation through a 10-inverters logic chain.Index Terms -Single event transient (SET), heavy-ion, temperature dependence, CMOS, LET, technology computeraided design (TCAD) simulation.Abstract-In this paper, a study by device simulation of the heavy-ion induced Single-Event Transients (SET) is realized in the 218 -418 K range in order to determine the temperature effect on a CMOS bulk 0.18 11m inverter. An investigation of the SET propagation though a 10-inverters logic chain is performed, and the threshold LET (LETth) required for unattenuated propagation through the inverters chain is determined. The LETth is calculated for two different location of the heavy ion impact and for three tern peratures. An increase of the sensitivity is found when the temperature raise from 218 to 418 K.

Temperature Dependence of Spatially Resolved Picosecond Laser Induced Transients in a Deep Submicron CMOS Inverter

“…A total charge decreasing strongly with temperature was not observed by Guo et al, although the substrate doping of around cm [10] used there is probably quite different to that used here (judging by the relative collection lengths). The qualitative trend observed in our data also disagrees with that of Truyen et al [11] and does in fact suggest a marked drop in minority carrier diffusion length at higher temperatures, which did actually occur in the Guo et al data, but to a much reduced extent.…”

“…That being the case, it stands to reason that increased pulse widths at higher temperatures can be expected to result in a higher DSET propagation cross-section. Truyen et al have in fact simulated DSET generation and propagation in the ATMEL 180 nm process from approximately 200 K to 400 K using 3D TCAD simulation [11]. In that work, DSET cross-sections did indeed increase several fold at higher temperatures.…”