Temperature-Independent Gate-Oxide Degradation Monitoring of SiC MOSFETs Based on Junction Capacitances

Farhadi, Masoud; Yang, Fei; Pu, Shi; Vankayalapati, Bhanu Teja; Akin, Bilal

doi:10.1109/tpel.2021.3049394

Cited by 42 publications

(7 citation statements)

References 75 publications

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“…Note that

consists of the overlap capacitance of the gate electrode with source plus channel region and the parallel capacitance across the gate and source metallization (

) [ 20 ];

in the active area of a 650

SiC MOSFET is addressed as

where

is the total length of the overlap between gate and

source and the channel region and

is the inter-layer dielectric capacitance, which stays constant for all the devices due to the same fabrication process being used for wafers 1 and 2.…”

Section: Device Characteristics and Discussionmentioning

confidence: 99%

Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs

et al. 2022

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650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal P+ layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The devices were packaged into open-cavity TO-247 packages for evaluation. Trade-off analysis of the static and dynamic performance of the 650 V SiC power MOSFETs was conducted. The measurement results show that a short JFET region with an enhanced JFET doping concentration reduces specific ON-resistance (Ron,sp) and lowers the gate-drain capacitance (Cgd). It was experimentally shown that a thinner gate oxide further reduces Ron,sp, although with a penalty in terms of increased Cgd. A design with 0.5 μm half JFET width, enhanced JFET doping concentration of 5.5×1016 cm−3, and thin gate oxide produces an excellent high-frequency figure of merit (HF-FOM) among recently published studies on 650 V SiC devices.

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“…Note that

consists of the overlap capacitance of the gate electrode with source plus channel region and the parallel capacitance across the gate and source metallization (

) [ 20 ];

in the active area of a 650

SiC MOSFET is addressed as

where

is the total length of the overlap between gate and

source and the channel region and

is the inter-layer dielectric capacitance, which stays constant for all the devices due to the same fabrication process being used for wafers 1 and 2.…”

Section: Device Characteristics and Discussionmentioning

confidence: 99%

Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs

et al. 2022

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“…The kelvin-source impedance is presented for package degradation monitoring which is only applicable for 4pin devices with the Kelvin connection [74]. The device's thermal impedance [75], saturation current [76], and miller capacitance [77] are other parameters for aging monitoring. These precursors can hardly be used for online tracking.…”

Section: Precursor Selection For Condition Monitoringmentioning

confidence: 99%

“…However, the package degradation at lower currents does not affect the body diode voltage. The body diode voltage at lower current is highly On-Resistance, (Rds,ON ) [82]- [84] Threshold Voltage, (Vth) [77], [83], [85] 2.4 mΩ/ • C for vendor A 1.6 mΩ/ • C for vendor B -6.4 mV/ • C for vendor A -3.1 mV/ • C for vendor B -Needs synchronized measurement for drain-source voltage and drain current.…”

Section: Junction Temperature Measurementmentioning

confidence: 99%

AC Power Cycling Test Setup and Condition Monitoring Tools for SiC-Based Traction Inverters

Farhadi

Vankayalapati

Sajadi

et al. 2023

IEEE Trans. Veh. Technol.

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AC power cycling tests allow the most realistic reliability assessment by applying close to real stress to the device or module under test to meet functional safety standards, which is highly critical for traction applications. This paper presents a comprehensive guideline and shares critical know-how to develop a 120 KVA AC power cycling test setup for high-power Silicon Carbide (SiC) modules. As of today, traction applications can not generate an early warning signal for drivers to replace critical components on time. For this purpose, the suitable precursors for all dominant failure mechanisms are discussed, and the corresponding condition monitoring tools are proposed to monitor the device aging on power converters. These condition monitoring tools are integrated into the built-in desaturation protection circuit of the electric vehicle (EV) gate driver for low-cost, practical implementation. The on-resistance of all twelve switches is monitored online as a temperature-sensitive electrical parameter (TSEP) to measure the junction temperature of the devices. To avoid heavy processing load in the microcontroller, the out-of-order equivalent time sampling technique is developed for data sampling, which leads to a measurement error of less than 1.5%. In addition, the design considerations regarding common mode noise and aging effect on DESAT protection are investigated, and experimental findings are presented.

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“…During each switching commutation, these dielectric materials are subjected to high electric fields stresses causing conducted leakage current through the insulation material due to the capacitive couplings, over time this can degrade the insulation properties of the dielectric materials [92]. In [93] a correlation between gate oxide degradation and the MOSFET intrinsic capacitive couplings are reported, where it is proposed to use the MOSFET change in capacitance as a precursor to the gate oxide degradation, however the mechanisms behind the proposed correlation are unclear. Another phenomenon related to the insulation degradation in PEC systems is the partial discharge phenomenon, which in various studies have been documented to cause long term degradation of dielectric material insulation properties [94]- [96].…”

Section: Reliability and Thermal Stressesmentioning

confidence: 99%

Parasitic Capacitive Couplings in Medium Voltage Power Electronic Systems: An Overview

Kjærsgaard

Liu

Nielsen

et al. 2023

IEEE Trans. Power Electron.

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show abstract

Temperature-Independent Gate-Oxide Degradation Monitoring of SiC MOSFETs Based on Junction Capacitances

Cited by 42 publications

References 75 publications

Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs

Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs

AC Power Cycling Test Setup and Condition Monitoring Tools for SiC-Based Traction Inverters

Parasitic Capacitive Couplings in Medium Voltage Power Electronic Systems: An Overview

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