Temporal redundancy latch-based architecture for soft error mitigation

Schmidt, Robert; García-Ortiz, Alberto; Fey, Görschwin

doi:10.1109/iolts.2017.8046245

Cited by 6 publications

(6 citation statements)

References 12 publications

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“…fi Finally, the boundary model is reused again for the new value of AVF mix ðECCÞ calculation in Eq (4) and Eq (5). w err denotes the error rate in the ECC mapped new model M new in Eq (4).…”

Section: Proposed Virtual Filter Based Assessment Methodologymentioning

confidence: 99%

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A virtual filter based fast assessment methodology for fault tolerant NoCs

Jiao

Han

2018

IEICE Electron. Express

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Network on Chips (NoCs) as the compromising communication infrastructures in many-core system, are suffering the serious Multi-Cell Upsets (MCU) impacts. To accelerate the accurate assessment of the increasing and complex MCU in fault tolerant NoCs, we propose a virtual filter based analytical methodology. The approach converts an original MCU model to a new regenerated MCU model via fault tolerance filtering, and then maps the new MCU information into an existing boundary model to estimate the effectiveness of fault tolerant schemes fast. The diverse results demonstrate that the virtual filter based assessment achieves 473.75× speedup and only 11.454% accuracy loss over the latest fault injection.

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Section: Proposed Virtual Filter Based Assessment Methodologymentioning

confidence: 99%

“…They take up half of area in a router [3] and vulnerable to MCU faults. Diverse fault tolerant schemes are used to protect the VCs from soft errors, e.g., redundancy strategies [4] and error codes for NoCs [5]. The accurate and fast estimation issue is critical for an early NoC design and dynamic reliable NoC configurations.…”

Section: Introductionmentioning

confidence: 99%

A virtual filter based fast assessment methodology for fault tolerant NoCs

Jiao

Han

2018

IEICE Electron. Express

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“…Dual modular redundancy [26] and error detection codes like parity [27] are hardware-based error detection techniques which exploit spatial redundancy to detect errors. Detection based on temporal redundancy is possible as well, and allows to trade performance for reliability and energy savings [28], [29].…”

Section: Related Workmentioning

confidence: 99%

Service Improvements in Real-Time Uniprocessor Scheduling With Single Errors

Schmidt

García-Ortiz

2021

IEEE Access

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Mixed-criticality scheduling in modern deeply embedded mission and safety-critical systems needs to consider delivered service, that is, the runtime in low criticality mode. If the change into a higher criticality mode is triggered by the first overrunning job, the service is severely reduced. With earliest deadline first with virtual deadlines for single errors (EDF-VD-SE) we show how to reserve additional time to tolerate a single overrunning job by formulating and solving an optimization problem, and that EDF-VD-SE is feasible without assumptions about error probabilities for safety guarantees. We conduct extensive simulation experiments to report on average doubled service figures, and show how EDF-VD-SE results in a nearly constant acceptance rate of random task systems.

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“…32 Unfortunately, TMR results in a more than 3x power, area and speed penalty due to the voters and long interconnects. To alleviate these drawbacks, several alternatives are possible 33,34 Instead of logic level triplication, these individual gates can be hardened At system level less generic and more specific mitigation is used. For instance, processors can use software level mitigation like signatures or tightly coupled cores, executing the same program.…”

Section: Introductionmentioning

confidence: 99%

Low-power electronic technologies for harsh radiation environments

et al. 2021

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Over the past decades, electronic technologies have evolved to serve a wide range of applications, with some necessitating their reliable operation in harsh radiation environments. This perspective article reviews the current landscape in rad-hard electronics, covering the scope of radiation environments, the application needs, the underlying phenomena that impose functional constraints as well as established design methodologies, relying on commercially available technologies (CMOS) for mitigating e↵ects that lead to failure. We further examine the potential of emerging memristive technologies in this field and their properties that render these rad-hard. We also review a variety of rad-hard device designs, rad-mitigation techniques, and experimental procedures for validating the performance of the most promising solutions. Finally, we conclude this article by presenting a roadmap on new concepts and application opportunities enabled by the introduction of novel technologies and designs that can reliably operate under such extreme conditions. topilot upsets that occur on average once in every 200 flight hours, notwithstanding, electrical upsets in automotive electronics and data centers. 3,7 In addition, the solar flares' intense particles and X-rays ionize and increase the density of the low layers of ionosphere, respectively, and interact with the electromagnetic waves resulting into disturbances in the high-frequency radio communication system by fading of the HF signal. 3 These problems eventually a↵ect the stability of the flight system, and tra c operations and navigations both in airspace and on the ground, where safety assurance is of primary importance. Similarly, the operation of nuclear facilities in a safety critical manner is of paramount importance and rad-hard technologies are commonly employed to enhance the overall safety margins. 8 Moreover, radiation e↵ects raise a concern in medical and industrial equipment where X-ray and are used for therapy and diagnostic purposes while in highenergy physics facilities, various particles and photons are generated by the collisions in particle accelerators which pose a severe challenge for the accelerator instrumentation and the radiation detection, data acquisition and communication in the embarked experiments. 9Nevertheless, rad-hard integrated circuit technologies often require additional processing and more complex configurations than the standard fabrication flow that makes the rad-hard electronics, particularly low-power electronic technologies, di cult to keep up with the International Technology Roadmap for Semiconductors (ITRS) guide. 10 This article examines the latest logic and memory design techniques for radiation e↵ect mitigation and presents future trends for rad-hard technologies.

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Temporal redundancy latch-based architecture for soft error mitigation

Cited by 6 publications

References 12 publications

A virtual filter based fast assessment methodology for fault tolerant NoCs

A virtual filter based fast assessment methodology for fault tolerant NoCs

Service Improvements in Real-Time Uniprocessor Scheduling With Single Errors

Low-power electronic technologies for harsh radiation environments

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