Temporal Refinement Using SMT and Model Checking with an Application to Physical-Layer Protocols

Brown, Geoffrey; Pike, Lee

doi:10.1109/memcod.2007.371227

Cited by 4 publications

(8 citation statements)

References 15 publications

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“…Note that in Section 6, we showed how to refine a finite-state specification into a infinitestate real-time implementation. We were able to prove liveness of the finite-state specification, but as noted by an anonymous reviewer of a recent paper by the authors [BP07], refinement does not preserve liveness.…”

Section: Soundnessmentioning

confidence: 89%

“…One implementation of infinite-bmc induction is in SRI International's Symbolic Correspondence and offprint requests to: geobrown@cs.indiana.edu, leepike@gmail.com Based on material originally published in [BP06] and on "Temporal Refinement Using SMT and Model Checking with an Application to Physical-Layer Protocols" by Brown and Pike which appears in "The Proceedings of the Fifth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'07)" c 2007 IEEE. [BP07] Analysis Laboratory (SAL) [dMOR + 04]. In this paper, we apply infinite-bmc induction to easily prove the correctness of a class of real-time protocols.…”

Section: Introductionmentioning

confidence: 99%

“…Anonymous reviewers provided valuable comments on the conference papers upon which this article is based [BP06,BP07] as well as this article.…”

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confidence: 99%

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Automated verification and refinement for physical-layer protocols

Brown

Pike

2011

Form. Asp. Comput.

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Abstract. This paper demonstrates how to use a satisfiability modulo theories (SMT) solver together with a bounded model checker to verify properties of real-time physical layer protocols. The method is first used to verify the Biphase Mark protocol, a protocol that has been verified numerous times previously, allowing for a comparison of results. The techniques are extended to the 8N1 protocol used in universal asynchronous receiver transmitters (UARTs). We then demonstrate the use of temporal refinement to link a finite state specification of 8N1 with its real-time implementation. This refinement relationship relieves a significant disadvantage of SMT approaches-their inability to scale to large problems. Finally, capturing the impact of metastability on timing requirements is a key issue in modeling physical-layer protocols. Rather than model metastability directly, a contribution of our models is treating its effect as a constraint on non-determinism.

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Section: Soundnessmentioning

confidence: 89%

Section: Introductionmentioning

confidence: 99%

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Automated verification and refinement for physical-layer protocols

Brown

Pike

2011

Form. Asp. Comput.

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“…are all available at http://sal.csl.sri.com. With my coauthors, I have had the opportunity to use SAL in a number of applied verifications [3,4,5,20,21,22]. 2 These works draw from the domains of distributed systems, fault-tolerant protocols, and asynchronous hardware protocols (the most notable omission is the domain of software, although the techniques reported are not domain-specific).…”

Section: Sri's Symbolic Analysis Laboratory (Sal)mentioning

confidence: 99%

“…The first example is drawn from work done with Geoffrey Brown to verify real-time physical-layer protocols [3,5]. Suppose I want to nondeterministically update some value to be within a parameterized closed interval of real-time (modeled by the real number line).…”

Section: Sets and Nondeterminismmentioning

confidence: 99%

Model checking for the practical verificationist

Pike

2007

Proceedings of the Second Workshop on Automated Formal Methods

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SRI's Symbolic Analysis Laboratory (SAL) is a high-level language-interface to a collection of state-of-the-art model checking tools. SAL contains novel and powerful features, many of which are not available in other model checkers. In this experience report, I highlight some of the features I have particularly found useful, drawing examples from published verifications using SAL. In particular, I discuss the use of higher-order functions in model checking, infinitestate bounded model checking, compositional specification and verification, and finally, mechanical theorem prover and model checker interplay. The purpose of this report is to expose these features to working verificationists and to demonstrate how to exploit them effectively.

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Complete Formal Hardware Verification of Interfaces for a FlexRay-Like Bus

Müller

Paul

2011

Computer Aided Verification

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We report in this thesis the first complete formal verification of a bus interface at the gate and register level. The presented bus interface allows to implement a timetriggered system consisting of several units interconnected by a bus. Time-triggered systems work decentralized, allow some grade of fault-tolerance against a bounded number of single errors and show a predictable recurrent behaviour. We use a hardware model for multiple clock domains obtained by formalization of data sheets for hardware components, and we review known results and proof techniques about the essential components of such bus interfaces: among others serial interfaces, clock synchronization and bus control. Combining such results into a single proof leads to an amazingly subtle theory about the realization of direct connections between units (as assumed in existing correctness proofs for components of interfaces) by properly controlled time-triggered buses. It also requires an induction arguing simultaneously about bit transmission across clock domains, clock synchronization and bus control. 1 The design of the bus controller can be automatically translated into Verilog and deployed on FPGAs. Zusammenfassung In dieser Arbeit präsentieren wir die erste formale Verifikation einer Bus-Schnittstelle auf der Register-und Gatter-Ebene. Die Bus-Schnittstelle ermöglicht die Implementierung eines zeitgesteuerten Systems, welches aus mehreren Einheiten besteht, die durch einen Bus verbunden sind. Systeme dieser Art funktionieren dezentralisiert, sind fehlertolerant gegen einzelne System-und Umgebungsfehler und weisen ein berechenbares periodisches Verhalten auf. Wir benutzten ein Hardware-Model für mehrere Clock-Domänen, welches durch die Formalisierung der Herstellungsinformationen abgeleitet wurde. Wir präsentieren verschiedene Ergebnisse und Verifikationstechniken über die essentiellen Komponenten solcher Bus-Schnittstellen: serielle Schnittstellen, Clock-Synchronisierung, Bus-Kontrolle, usw. Die Kombination solcher Ergebnisse zu einem einzigen Korrektheitsbeweis führt zu einer nicht-triviallen Theorie über die Realisierung einer direkten Verbindung zwischen verschiedenen Einheiten des Systems (wie das in den einzelnen Beweisen verschiedener Komponente angenommen wird), die auf einer korrekten Kontrolle zeitgesteuerter Busse basiert. Die Korrektheit der gesamten Schnittstelle ergibt sich aus einem Induktionsbeweis, der gleichzeitig über drei Eigenschaften argumentiert: über die Signalübertragung zwischen unterschiedlichen Clock-Domänen, über die Clock-Synchronisierung und über die zeitlich-korrekte Einteilung der Bus-Zugriffe. Die Implementierung kann automatisch in Verilog-Code übersetzt werden und auf

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Temporal Refinement Using SMT and Model Checking with an Application to Physical-Layer Protocols

Cited by 4 publications

References 15 publications

Automated verification and refinement for physical-layer protocols

Automated verification and refinement for physical-layer protocols

Model checking for the practical verificationist

Complete Formal Hardware Verification of Interfaces for a FlexRay-Like Bus

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