Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness*

Abstract

A novel terminal-optimized triple RESURF LDMOS (TOTR-LDMOS) is proposed and verified in a 0.25-μm bipolar-CMOS-DMOS (BCD) process. By introducing a low concentration region to the terminal region, the surface electric field of the TOTR-LDMOS decreases, helping to improve the breakdown voltage (BV) and electrostatic discharge (ESD) robustness. Both traditional LDMOS and TOTR-LDMOS are fabricated and investigated by transmission line pulse (TLP) tests, direct current (DC) tests, and TCAD simulations. The results show that comparing with the traditional LDMOS, the BV of the TOTR-LDMOS increases from 755 V to 817 V without affecting the specific on-resistance (R on,sp) of 6.99 Ω⋅mm2. Meanwhile, the ESD robustness of the TOTR-LDMOS increases by 147%. The TOTR-LDMOS exhibits an excellent performance among the present 700-V LDMOS devices.

Degradation and breakdown behaviors of SGTs under repetitive unclamped inductive switching avalanche stress

“…Apart from some essential models (e.g., doping dependency, high field velocity saturation, Shockley-Read-Hall recombination and Auger recombination), bandgap narrowing and UNIBO avalanche model are considered. [10] Figure 4 shows the simulated avalanche current flow path and impact ionization (I.I.) distribution of C-SGT and P-SGT.…”

Review of the SiC LDMOS power device

“…Numerous investigations have demonstrated that the maximum electric field in LDMOS power devices is predominantly concentrated at the drain side adjacent to the gate edge. This highlights that this particular point is highly susceptible to high drain voltage [38][39][40][41][42][43] . Therefore, to increase the breakdown voltage, it becomes imperative to mitigate the peak electric field and achieve a more uniform surface electric field.…”