Test case verification by model checking

Naik, Kshirasagar; Sarikaya, Behçet

doi:10.1007/bf01384135

Cited by 5 publications

(5 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, verifying CPS HiL test cases and estimating their execution times have not been studied much in the existing work. Naik and Sarikaya [32] use model checking to verify test cases developed for testing protocols. In their work, test case behaviors are expressed using extended state machines, and verified against safety and liveness properties formalized in temporal logic.…”

Section: Related Workmentioning

confidence: 99%

Hitecs

Shin

Chaouch

Nejati

et al. 2018

Proceedings of the 21th ACM/IEEE International Conference on Model Driven Engineering Languages and Systems

View full text Add to dashboard Cite

Hardware-in-the-loop (HiL) testing is an important step in the development of cyber physical systems (CPS). CPS HiL test cases manipulate hardware components, are time-consuming and their behaviors are impacted by the uncertainties in the CPS environment.To mitigate the risks associated with HiL testing, engineers have to ensure that (1) HiL test cases are well-behaved, i.e., they implement valid test scenarios and do not accidentally damage hardware, and (2) HiL test cases can execute within the time budget allotted to HiL testing. This paper proposes an approach to help engineers systematically specify and analyze CPS HiL test cases. Leveraging the UML profile mechanism, we develop an executable domainspecific language, HITECS, for HiL test case specification. HITECS builds on the UML Testing Profile (UTP) and the UML action language (Alf). Using HITECS, we provide analysis methods to check whether HiL test cases are well-behaved, and to estimate the execution times of these test cases before the actual HiL testing stage. We apply HITECS to an industrial case study from the satellite domain. Our results show that: (1) HITECS is feasible to use in practice;(2) HITECS helps engineers define more complete and effective wellbehavedness assertions for HiL test cases, compared to when these assertions are defined without systematic guidance; (3) HITECS verifies in practical time that HiL test cases are well-behaved; and (4) HITECS accurately estimates HiL test case execution times. CCS CONCEPTS• Software and its engineering → Model-driven software engineering; Specification languages; Software verification and validation;

show abstract

Section: Related Workmentioning

confidence: 99%

Hitecs

Shin

Chaouch

Nejati

et al. 2018

Proceedings of the 21th ACM/IEEE International Conference on Model Driven Engineering Languages and Systems

View full text Add to dashboard Cite

show abstract

“…where the procedure Exec returns those transitions from s whose enabling conditions evaluate to true [NS93].…”

Section: -1 Timed Reachability Analysismentioning

confidence: 99%

“…If the transition is an internal transition then the PCO predicate INTERNAL is associated. For all other transitions the NULL predicate is associated (NS93].…”

Section: -1 Timed Reachability Analysismentioning

confidence: 99%

“…Based on the idea that nothing bad happens during a test case execution, the safety properties of a test case can be classified into three distinct categories [NS93]: transmission safety, reception safety, and verdict safety. All of the above properties can be expressed using the temporal formula corresponding to the following two constructs in timed-CSP: CONS!…”

Section: Temporal Formula For Safetymentioning

confidence: 99%

“…These test suites may, however, contain several errors [BS93]. Therefore interest in verification of these test suites using formal specification of the protocol is growing [DB90,NS93]. Standards organizations have defined various formal specification languages such as SDL [CCI92].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Protocol Conformance Test Case Verification Using Timed-Transitions

Naik

Sarikaya

1995

IFIP Advances in Information and Communication Technology

Self Cite

View full text Add to dashboard Cite

We develop a methodology to verify the correctness of test cases designed to check timed behavior of protocol implementations. The verification process consists of four steps. First, we model a protocol specification, a test case, and an underlying service provider as Timed Extended Finite-State Machines (TEFSM) and define the resulting system as a Test Verification System (TVS). Next, we algorithmically obtain a model, i.e., a predicated global state space, from the TVS. Test case properties are formulated in terms of safety and liveness using branching time temporal logic. Finally we verify the test case properties on the model of the TVS using a model checking algorithm. We apply the verification technique to a test case for the Inres protocol. A few errors are detected in the design of the test case. We observe that without the use of TEFSM model, it would not have been possible to detect any time related errors in the test case.

show abstract