Test chip characterization of X architecture diagonal lines for SoC design

Arora, N.D.; Song, Li; Shah, S.; Joshi, Ketan; Thumaty, K.; Fujimura, Aki; Schoellkopf, J.-P.; Brut, H.; Smayling, Michael C.; Nagata, Toshiyuki

doi:10.1109/icmts.2004.1309305

Cited by 6 publications

(4 citation statements)

References 3 publications

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“…Overall, the standard deviations of X Architecture are comparable to those of Manhattan structure. The average effective line width is slightly higher in the X Architecture design, partly due to the higher drawn width (0.1414 m) of the X Architecture vs. Manhattan structure (0.14 m) [3].…”

Section: Test Structure Resultsmentioning

confidence: 99%

“…The test chip consists of structures of comb/serpentine, maze, via chain, as well as resistance and capacitance structures that are used to study the electrical properties (resistance and capacitance) of diagonal wires. They were designed using both 90nm and 65nm Cu CMOS processes [2,3]. Comb/serpentine (CS) test structures consist of four quadrants (Figure 2a), all having 2 combs and a serpentine traversing around these combs.…”

Section: Test Structurementioning

confidence: 99%

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Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes

Song

Chen²,

Shah

et al. 2005

Design and Process Integration for Microelectronic Manufacturing III

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The X Architecture offers the potential to produce smaller and faster integrated circuits through the pervasive use of 45 wirings on the upper metal layers. The X Initiative members have demonstrated its manufacturability and integrationworthiness at the 130nm, 90nm and 65nm process technology nodes. This paper explores the use of off-axis lithography illumination to print 45 diagonal wires at leading technology nodes. The paper also describes the RET strategies employed for the X Architecture and the effectiveness of various illumination sources at various process nodes. Process window and metal wiring CD variation of Manhattan and X Architecture are compared in the simulations using different types of illuminators. Simulation shows that using 193nm light source, Manhattan and X designs can easily be printed with different types of illuminating source in either 90nm or 65nm process node. Silicon test chips at 90nm that include typical X routing patterns are designed to verify the printability of X Architecture wirings. Electrical measurements as well as SEM analysis are conducted and results show that the fidelity of diagonal wirings is as good as traditional Manhattan routings.

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Section: Test Structure Resultsmentioning

confidence: 99%

Section: Test Structurementioning

confidence: 99%

Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes

Song

Chen²,

Shah

et al. 2005

Design and Process Integration for Microelectronic Manufacturing III

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show abstract

“…Arora et al 7 used these so-called Telegrapher's equations to determine the resistance and inductance per unit length of a selection of interconnect-line implementations over frequencies ranging from 10 GHz to 50 GHz. Our approach uses the same microwave-engineering mathematics to extract the signal and ground line's CDs by cross-referencing the measured values of characteristic impedance and distributed capacitance to a listing of their values that are derived from electromagnetic field modeling, according to the description that follows.…”

Section: Cpw Basics: Extracting Characteristic Impedance and Distribumentioning

confidence: 99%

“…6 The fundamentals of a basic CPW architecture consistent with the COG application are shown schematically in Figure 1. § Arora et al 7 have reported the use of CPW test structures for investigating the radio-frequency (RF) impedances of on-chip interconnect features having various architectures. In the implementation proposed here, which follows the Arora approach, the first task is to measure the S-parameters, S 11 , S 12 , S 21 , and S 22 , of the as-replicated CPW test structure with a network analyzer and compute from the measurements the CPW's characteristic impedance Z and its propagation constant .…”

Section: Cpw Basics: Extracting Characteristic Impedance and Distribumentioning

confidence: 99%

A new critical dimension metrology for chrome-on-glass substrates based on s-parameter measurements extracted from coplanar waveguide test structures

et al. 2006

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The technical objective of the work reported here is to assess whether radio-frequency (RF) measurements made on coplanar waveguide (CPW) test structures, which are replicated in conducting material on insulating substrates, could be employed to extract the critical dimension (CD) of the signal line using its center-to-center separation from the groundlines as a reference. The specific near-term objective is to assess whether this CPW-based CD-metrology has sensitivity and repeatability competitive with the other metrology techniques that are now used for chrome-on-glass (COG) photomasks. An affirmative answer is encouraging because advancing to a non-contact and non-vacuum implementation would then seem possible for this application. Our modeling of specific cases shows that, when the pitch of the replicated lines of the CPW is maintained constant, the sensitivity of its characteristic impedance to the CDs of the signal and ground lines is approximately 60 /µm. This is a potentially useful result. For the same implementation, the quantity C/ w has a value of approximately 45 (pF/m)/µm, which appears to be large enough to provide acceptable accuracy. BACKGROUND AND OBJECTIVEIn photomask mask fabrication, critical dimension (CD) metrology is typically conducted by optical transmission, Scanning Electron Microscopy (SEM), and Atomic Force Microscopy (AFM) tools. These have different advantages and limitations. A metrology implementation that is not so widely known as these three techniques is electrical CD (ECD) metrology, a variation of which is the subject of this paper. There are prior reports on the extraction of geometrical information from the features of test structures replicated on chrome-on-glass (COG) masks by electrical means. For example, one approach was to probe electrical test structures that were patterned in chrome and were then tested in a dc mode. 1 In the cited report, an important innovation was providing for the electrical-length shortening of the bridge of a test structure that was configured as a micro-potentiometer. There were provisions in the test-structure design for the extraction of a parameter named L that characterized the micro-geometry of the intersection of two features. The V/I values of the two segments of the bridge of the micro-potentiometer were extracted with Kelvin voltage taps, which enabled managing the effect of contact resistance. 2 The measured resistance values of the bridge were then used to estimate the center-to-center separations of parallel features serving as voltage taps to the bridge more accurately than had been otherwise possible as a result of correcting the physical length of each segment of the bridge † Official contribution of the

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Test chip for inductance characterization and modeling for sub-100nm X architecture and Manhattan chip design

Arora

Song

Shah

et al.

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005.

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Test chip characterization of X architecture diagonal lines for SoC design

Cited by 6 publications

References 3 publications

Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes

Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes

A new critical dimension metrology for chrome-on-glass substrates based on s-parameter measurements extracted from coplanar waveguide test structures

Test chip for inductance characterization and modeling for sub-100nm X architecture and Manhattan chip design

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