Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation

Abstract

This paper presents a test compression method that effectively derives the capability of a run-length based encoding. The method employs two techniques: scan polarity adjustment and pinpoint test relaxation. Given a test set for a full-scan circuit, scan polarity adjustment selectively flips the values of some scan cells in test patterns. It can be realized by changing connections between two scan cells so that the inverted output of a scan cell, Q, is connected to the next scan cell. Pinpoint test relaxation flips some specified 1s in the test patterns to 0s without any fault coverage loss. Both techniques are applied by referring to a gain-penalty table to determine scan cells or bits to be flipped. Experimental results on ISCAS' 89 benchmark circuits show that the proposed method could reduce test data volume by 36%. Switching activities, i.e. test power during scan testing, were also reduced.

A diagnosis algorithm for extreme space compaction

“…Sophisticated techniques for handling the input side of embedded test schemes are published and available on the market. They include continuous reseeding [13], [14], embedded deterministic testing [15], [16], [17], [18]. For masking unknown values prior to parity compaction, several well-known techniques including [19], [20], [21] are applicable here.…”