Test cost reduction for logic circuits: Reduction of test data volume and test application time

Abstract

SUMMARYWe believe that reduction of the testing cost is becoming increasingly important as the size of VLSIs becomes larger. Moreover, as the structure of VLSIs becomes more complicated, test compaction, test compression, and test application time reduction for non-stuck-at faults, such as delay faults, bridging faults, crosstalk faults, and open faults, must be considered. In addition, new methods of fault diagnosis and high-level testing must be developed in order to reduce testing costs or diagnostic costs. In this paper we have surveyed recent research on the reduction of testing cost for logic circuits, including test compaction for combinational circuits and sequential circuits, test compaction under IDDQ testing, and test compression and test application time reduction for scan circuits.

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits

“…Sequence T 0 detects 3 faults f 1 , f 2 and f 3 , and f 1 , f 2 and f 3 are detected by v 3 , v 4 and v 7 , respectively. Table III shows an FDETT for T 0 .…”

“…This is primarily due to the fact that testing large scale circuits requires a large number of test vectors which in turn increase the test application time, tester memory space, and hence the total test cost. Numerous research papers have proposed various compaction techniques to reduce the number of test vectors and the volume of test data [4]. In particular, [8] studied the effect of detection-oriented test compaction on fault diagnosis experimentally and showed the loss of diagnosis capability of such methods.…”

Reducing test application time, test data volume and test power through Virtual Chain Partition

“…Test time and test storage are the main problems to be taken into account for SoCs [17]. Input reduction techniques based on relations of compatibility between the circuit inputs allow both the number of test application cycles and the number of memory bits required for their storage to be reduced [13]. A mapping logic allows the n-bit patterns generated by the test pattern generator (TPG) to be transformed into patterns for the m4n MUT inputs.…”