Test Coverage Analysis for Designs with Timing Exceptions

Tsai, Kun-Han; Gopalakrishnan, Srinivasan

doi:10.1109/ats.2017.41

Cited by 4 publications

(2 citation statements)

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“…Meanwhile, fault cones have previously been studied in the context of multiple applications (e.g. [3,9,23,29,30,37,44,46]). For example, based on fault cones, [37] proposed a new method to obtain various distinct propagation paths for faults for n-detect.…”

Section: Previous Workmentioning

confidence: 99%

“…The authors of [44] introduced a method to test failures caused by replacing or cascading gates incorrectly in reversible circuits with fault cones. The researchers in [46] investigated extra constraints during test generation i.e. constraints for timing exceptions to ensure the correctness of the pattern set) to improve test coverage decreased by timing exceptions, where fault cones helped in finding the hard timing exceptions.…”

Section: Previous Workmentioning

confidence: 99%

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Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift

et al. 2023

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Test sets that target standard fault models may not always be sufficient for detecting all defects. To evaluate test sets for the detection of unmodeled defects, n-detect test sets (which detect all modeled faults at least n times) have previously been proposed. Unfortunately, n-detect test sets are often prohibitively long. In this paper, we investigate the ability of shadow flip-flops connected into a MISR (Multiple Input Signature Register) to detect stuck-at faults fortuitously multiple times during scan shift. We explore which flip-flops should be shadowed to increase the value of n for the least detected stuck-at faults for each circuit studied. We then identify which circuit characteristics are most important for determining the cost of the MISR needed to achieve high values of n. For example, circuits that contain a few flip-flops with upstream fault cones that cover a large percentage of all faults in the circuit can often achieve high n-detect coverage fortuitously with a low-cost MISR. This allows a DFT engineer to predict the viability of this MISR-based approach early in the design cycle.

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