Test Data Compression and Power Reduction Using Similarity Based Reordering Technique for Wireless Systems

Harikumar, R.; Manjurathi, B.

doi:10.1007/s11277-016-3196-x

Cited by 3 publications

(1 citation statement)

References 19 publications

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“…In Double hamming distance-based 2D reordering, two dimensions of the test set (rows and columns) are considered for reordering the test vectors for effective compression [1]. Sokal and Sneath similarity coefficient is used for reordering the test set to improve the compression [2]. Weighted transition and hamming distance-based reordering were introduced by US Mehta [3][4][5]7].…”

Section: Introductionmentioning

confidence: 99%

An analysis of low power testing using K ‐means clustering with reordering approach

Jegannathan¹,

Rajaguru

2021

Electronics Letters

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K-means clustering is a machine learning algorithm used to group the data based on the similarity between the data. Functional distances like squared Euclidean distance, city block, cosine, correlation and hamming are considered as a similarity parameter here. Test vectors are grouped based on the functional distance using the K-means algorithm. A simple reordering algorithm is proposed and is applied to each group of data before 'X' bit filing to minimize the test power. Experimental results on ISCAS 89 benchmark circuit shows that the proposed methods diminish the power effectively.

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Section: Introductionmentioning

confidence: 99%

An analysis of low power testing using K ‐means clustering with reordering approach

Jegannathan¹,

Rajaguru

2021

Electronics Letters

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An algorithmic approach for minimizing test power in VLSI circuits

Poornimasre¹,

Rajaguru²

2021

IOP Conf. Ser.: Mater. Sci. Eng.

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Testing is an approach to check the function of the circuit or device under the test after its fabrication. To test the device, test patterns are required. The test patterns can be generated with the help of EDA tool. Those patterns having huge number of unfilled bits. The unfilled bits need to be assigned with certain logical value. This paper proposed two new algorithms. First algorithm assigns the unfilled bits with effective logical value and second algorithm change the order of test set and both algorithms aims to reduce the test power. Investigation on benchmark circuits shows that, the results of proposed algorithms effectively reduces the test power.

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Hardware optimization for effective switching power reduction during data compression in GOLOMB rice coding

Sakthivel,

Vijayalakshmi,

Vanitha

et al. 2024

PLoS ONE

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Loss-less data compression becomes the need of the hour for effective data compression and computation in VLSI test vector generation and testing in addition to hardware AI/ML computations. Golomb code is one of the effective technique for lossless data compression and it becomes valid only when the divisor can be expressed as power of two. This work aims to increase compression ratio by further encoding the unary part of the Golomb Rice (GR) code so as to decrease the amount of bits used, it mainly focuses on optimizing the hardware for encoding side. The algorithm was developed and coded in Verilog and simulated using Modelsim. This code was then synthesised in Cadence Encounter RTL Synthesiser. The modifications carried out show around 6% to 19% reduction in bits used for a linearly distributed data set. Worst-case delays have been reduced by 3% to 8%. Area reduction varies from 22% to 36% for different methods. Simulation for Power consumption shows nearly 7% reduction in switching power. This ideally suggest the usage of Golomb Rice coding technique for test vector compression and data computation for multiple data types, which should ideally have a geometrical distribution.

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Test Data Compression and Power Reduction Using Similarity Based Reordering Technique for Wireless Systems

Cited by 3 publications

References 19 publications

An analysis of low power testing using K ‐means clustering with reordering approach

An analysis of low power testing using K ‐means clustering with reordering approach

An algorithmic approach for minimizing test power in VLSI circuits

Hardware optimization for effective switching power reduction during data compression in GOLOMB rice coding

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