Test Data Compression for System-on-a-Chip using Count Compatible Pattern Run-Length Coding

“…However, similar to previously proposed methods, it also did not improve data transmission. On the premise of not changing the coverage rate of the test fault, Yuan et al [27] introduced a count compatible pattern run-length (CCPRL) compressed coding method for test vector. Using their method, the test data compression ratio reached 71.73%, but it did not propose an effective optimization strategy for test data transmission after compression, thus failing to improve the test application time.…”

Section: State Of the Artmentioning

confidence: 99%

“…The commonly used test vector compressed coding methods include pattern run-lenth (PRL) code [11,12], Huffman code [13], false discovery rate (FDR) code [14,15], nine-coded (9C) code [16], block merging (BM) code [12,17], and extended frequency-directed run-length (EFDR) code [18,19]. These methods can effectively achieve good compression effect and reduce the storage cost of test data.…”

Section: Introductionmentioning

confidence: 99%

Test Stimuli Segmentation and Coding Method

2018

Teh. vjesn.

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Test vector coding and data transmission are the key technologies in the design-for-test of digital integrated circuits (IC). Existing parallel input methods of test stimuli can reduce test application times; however, they need to occupy multiple input ports. Thus, a novel method of test stimuli coding and data transmission was proposed to reduce the test application time of the test vectors and reduce the number of input ports required for the parallel input of test stimuli. This method was based on the segmentation of test stimuli. First, the test stimuli were evenly segmented into eight-bit wide. Second, the eight-bit data of each segment were encoded to the five-bit data according to the compatibility between the test data of each segment. The eight-bit test stimuli input can be completed in one or two clock cycles of automatic test equipment (ATE) by using the five input ports of the chip. The corresponding decoding circuit was added inside the netlist of the circuit to realize the rapid input of the test stimuli. Lastly, the ISCAS'89 benchmark circuit was used to conduct experiments, results of this coding method were then compared with those of the serial input method. Results show that the encoding method proposed in this study can save an average of 37% of the parallel input data width and 81.7% of the test stimuli input time. The proposed method in this study can also reduce the test application time and the cost of the IC test. The findings of this study can provide guidance for improving the scan testing method of digital IC.

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“…Next, the digital outputs are obtained from the analog outputs using analog-to-digital (ADC) sampling. Compared with conventional compression methods [12], this analog implementation of compressive sensing entails lower quantized noise as it converts the input signal to digital codes before compression [13,14].…”

Section: Compressive Sensing Technology and Hardware Schemementioning

confidence: 99%

Compressive Sensing Measurement Matrix Generator Based on Improved SC-Array LDPC Code

Yuan

Song

Sun

et al. 2015

Circuits Syst Signal Process

Self Cite

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We construct and implement a compressive sensing measurement matrix based on improved size-compatible (ISC)-array low-density parity-check (LDPC) code. First, we propose an improved measurement matrix from the array LDPC code matrix. The proposed measurement matrix retains suitable quasi-cyclic structures and supports arbitrary code lengths. It also achieves a high perfect recovery percentage compared with a Gaussian random matrix of the same size. Second, we propose a hardware scheme using cycle shift registers to design the compressive sensing measurement matrix generator. This provides simple circuit architecture during the generation of the measurement matrix. According to simulation verifications, the measurement matrix construction method is effective and entails fewer shift registers and a lower area overhead by using a simplified hardware implementation scheme. The compressive sensing measurement matrix generator can generate all of the required elements in Circuits Syst Signal Process the ISC-array LDPC code matrix with an acceptable hardware overhead. Therefore, it can be widely applied to large-scale sparse signal compressive sensing.

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Test Data Compression for System-on-a-Chip using Count Compatible Pattern Run-Length Coding

Cited by 14 publications

References 13 publications

A Power Efficient Test Data Compression Method on Count Compatible PRL Coding

A Power Efficient Test Data Compression Method on Count Compatible PRL Coding

Test Stimuli Segmentation and Coding Method

Compressive Sensing Measurement Matrix Generator Based on Improved SC-Array LDPC Code

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