Test data compression scheme based on variable-to-fixed-plus-variable-length coding

Zhan, Wei; Liang, Hongbin; Shi, Feng; Huang, Zhengfeng

doi:10.1016/j.sysarc.2007.02.006

Cited by 15 publications

(3 citation statements)

References 41 publications

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“…Researches about reducing test data volume fall into three aspects: Built-in Self-test (BIST) [1][2], test set compact [3], and test data compression [4][5][6][7][8]. Using BIST circuitry can reduce the test data volume, but the area overhead is not negligible [3] and the fault coverage of pseudorandom is also limited because many digital circuits contain Random Resistant Fault [6]. The target of test set compaction is to reduce the number of test vectors and achieve the same fault coverage, this technology does not introduce additional hardware overhead, but the coverage of unmolded defects is decreased.…”

Section: A Related Workmentioning

confidence: 99%

A test data compression scheme based on position information coding

Tian

Yang

Wang

et al. 2014

Fifth International Conference on Computing, Communications and Networking Technologies (ICCCNT)

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Under the condition of Built-off Self-test (BOST), a novel test data compression scheme based on position information coding is presented, which is targeting test data and test power consumption. The proposed scheme gets the next test stimuli by reversing some bits of the responses corresponding to the previous test vectors. During the process of bit flip, test power problem should be taken into account; both the shift power and capture power during the test should be limited in the scope of security. For shift power, need to modify the scan chain by adding blocking logic; and the capture power reduction through the test cube filling based on the response. Experimental results justify the efficacy of the proposed method in attaining test-data compression; the average compression ratio is 73.63% on the premise of capture power consumption reduced by 20%.

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Section: A Related Workmentioning

confidence: 99%

A test data compression scheme based on position information coding

Tian

Yang

Wang

et al. 2014

Fifth International Conference on Computing, Communications and Networking Technologies (ICCCNT)

View full text Add to dashboard Cite

show abstract

“…In 2007, Zhan et al [22] proposed a test data compression based on fixed-plusvariable-length (FPVL) coding. This scheme divides code word into two parts: fixed-length head section and variablelength tail section.…”

Section: Fixed-plus-variable-lengthmentioning

confidence: 99%

Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey

2010

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The run length based coding schemes have been very effective for the test data compression in case of current generation SoCs with a large number of IP cores. The first part of paper presents a survey of the run length based codes. The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In the second part of the paper, the five different approaches for "don't care" bit filling based on nature of runs are proposed to predict the maximum compression based on entropy. Here the various run length based schemes are compared with maximum data compression limit based on entropy bounds. The actual compressions claimed by the authors are also compared. For various ISCAS circuits, it has been shown that when the X filling is done considering runs of zeros followed by one as well as runs of ones followed by zero (i.e., Extended FDR), it provides the maximum data compression. In third part, it has been shown that the average test power and peak power is minimum when the don't care bits are filled to make the long runs of 0s as well as 1s.

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“…While testing, the compressed test vectors are sent to the decompressed circuit on the chip through test equipment, and through the decompression circuit, restore the test vectors whose corresponding specified position is the same with original test vectors, and applied it to tested circuit to complete the test. According to the original data and compressed data's volume's change relationship, Coding based compression technology can be divided into five categories: fixed-length to fixed-length coding method [3] , fixedlength to variable-length coding method [4,5] , variable-length to fixed-length coding method [6] , variablelength to variable-length coding method [7][8][9][10][11] , and mixed method of fixed and variable length [12][13][14] . This technique's advantages are independent of test circuit, and can operate directly on the test set, without the need to understand the internal structure of the test circuit.…”

Section: Introductionmentioning

confidence: 99%

A LFSR Reseeding Scheme Based on Division by 2 to the Power of Integer

Zhan¹,

Ma²,

Du³

et al. 2010

JDCTA

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As the number of specified bits of different test patterns varies widely in a deterministic test cube, all test patterns are concatenated to a data flow. The original test data can be re-divided by 2 to the power of integer according to the successful characteristics of the LFSR coding, whose length equals to the power of 2 in every division. In the new test approach, the numbers of specific bits in the new test vectors are very close. Hence the encoding efficiency can be enhanced in the process of LFSR. And experimental results show that the compression ratio of this scheme can improve 2.32 % than that of hybrid coding. Compared with the previous schemes, the proposed scheme can increase the encoding efficiency with simple decompression structure and less area overhead.

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Test data compression scheme based on variable-to-fixed-plus-variable-length coding

Cited by 15 publications

References 41 publications

A test data compression scheme based on position information coding

A test data compression scheme based on position information coding

Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey

A LFSR Reseeding Scheme Based on Division by 2 to the Power of Integer

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