Test-Delivery Optimization in Manycore SOCs

Abstract

We present two test-data delivery optimization algorithms for system-on-chip (SoC) designs with hundreds of cores, where a network-on-chip (NoC) is used as the interconnection fabric. We first present an effective algorithm based on a subsetsum formulation to solve the test-delivery problem in NOCs with arbitrary topology that use dedicated routing. We further propose an algorithm for the important class of NOCs with grid topology and XY routing. The proposed algorithm is the first to cooptimize the number of access points, access-point locations, pin distribution to access points, and assignment of cores to access points for optimal test resource utilization of such NOCs. Test-time minimization is modeled as an NoC partitioning problem and solved with dynamic programming in polynomial time. Both the proposed methods yield high-quality results and are scalable to large SOCs with many cores. We present results on synthetic grid topology NoC-based SOCs constructed using cores from the ITC'02 benchmark, and demonstrate the scalability of our approach for two SOCs of the future, one with nearly 1000 cores and the other with 1600 cores. Test scheduling under power constraints is also incorporated in the optimization framework.

ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

“…Since the power consumption of each core is not mentioned in the ITC'02 benchmark database, it was taken from [21]. For the proposed algorithm, it was assumed that SoCs have the similar NoC fabric as given in [9,15,17] including network topology, core placement etc.…”

“…Minimization of test time with the given pin count is well described here. In [15], test delivery optimization of many core systems is proposed. Here, NoC partitioning difficulty is formulated with dynamic programming.…”