Test economics for multi-site test with modern cost reduction techniques

Volkerink, E.; Khoche, A.; Rivoir, Jochen; Hilliges, K.D.

doi:10.1109/vts.2002.1011173

Cited by 55 publications

(31 citation statements)

References 5 publications

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“…In addition, the test architecture described in [39] is less efficient when the total number of TAM lines is small, because, in such a case, producer and consumer TAMs normally sit idle for a long time and hence these test resources are wasted. When multisite testing is utilized to reduce the SOC test cost [7], [18], [37], the number of TAM lines is usually small, which necessitates a better test strategy for this reduced-pin-count testing scenario [2], [38]. Furthermore, the test scheduling algorithm in [39] is more effective when the number of unwrapped logic blocks is large.…”

Section: B Related Workmentioning

confidence: 99%

Modular and rapid testing of SOCs with unwrapped logic blocks

Nicolici

2005

IEEE Trans. VLSI Syst.

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Abstract-Extensive research has been carried out for test planning of core-based system-on-a-chip devices. Most of the prior work assumes that all of the embedded cores are wrapped for test purpose. However, some designs may contain user-defined logic or cores that cannot be wrapped due to area constraints or timing violations. This paper discusses how these unwrapped logic blocks can be tested rapidly by adapting the TestRail architecture, which uses only the test control mechanism and the test instructions available through the IEEE 1500 standard for embedded core test. A new test scheduling algorithm, which facilitates a concurrent test of both unwrapped logic blocks and IEEE 1500-wrapped cores, is proposed, and experiments show that it outperforms a previous approach when the available number of tester channels and/or the number of unwrapped logic blocks are small.

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Section: B Related Workmentioning

confidence: 99%

Modular and rapid testing of SOCs with unwrapped logic blocks

Nicolici

2005

IEEE Trans. VLSI Syst.

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“…TAM optimization is performed to improve test access to embedded cores in a modular test environment [4,5,7]. Finally, multi-site test seeks to test several copies of the SOC simultaneously on the ATE, thus reducing testing time across an entire production batch [16]. While these methods increase the efficiency of ATE use, they assume that the ATE always operates at core scan chain frequencies.…”

Section: Implicit Test Costmentioning

confidence: 99%

Test cost reduction for SOCs using virtual TAMs and lagrange multipliers

Sehgal

Iyengar

Krasniewski

et al. 2003

Proceedings of the 40th Conference on Design Automation - DAC '03

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“…However the growing demand for automatic test equipment (ATE) resources during manufacturing test of SOCs has led to a sharp increase in test cost [16]. Test cost for large SOCs can be viewed as consisting of:…”

Section: Introductionmentioning

confidence: 99%