Test Generation for Open Defects in CMOS Circuits

Devta-Prasanna, Narendra; Gunda, A.; Krishnamurthy, P.; Reddy, S.M.; Pomeranz, Irith

doi:10.1109/dft.2006.62

Cited by 13 publications

(3 citation statements)

References 22 publications

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“…As we describe below, there is a second mechanism that can generate open fault activating hazards -these are focus of this work. The failure of LOC TDF tests to detect some potentially easily detectable transistor stuck-open defects was addressed in [6] by modifying the LOC TDF test generation requirements to additionally force a transition at the gate output when targeting TDFs at the transistor inputs. However, there were still a significant number of opens that remained undetected by this explicit procedure to target TSOFs, i.e.…”

Section: Background and Prior Workmentioning

confidence: 99%

Improving CMOS open defect coverage using hazard activated tests

Han

Singh

2014

2014 IEEE 32nd VLSI Test Symposium (VTS)

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Recent studies indicate that a significant number of very large delay faults that increase circuit path delays several fold, remain difficult to detect and are only discovered by very carefully crafted and comprehensive two-pattern tests, e.g. cell aware tests. A likely source of such large delays in CMOS is stuck-open faults. These can sometimes still allow the circuit to reach the correct logic values through the charging of the floating node by small leakage currents in the circuit, although with large delays. It is well known that many open defects are not covered by commonly employed TDF launch on capture (LOC) scan delay tests; the coverage of specially generated transistor stuckopen tests published in the literature is only modestly better. It is commonly assumed that such undetected open faults are benign because the circuit states needed to activate them cannot be reached in normal functional operation. However, traditional test generation only considers final "steady state" signal values and ignores transients. In practice CMOS circuits experience many more transient states from the large number of hazards that occur during switching transitions. Many undetected open defects can be activated by such hazards during normal operation and cause a functional error. Such open faults must be detected by tests targeting low DPPMs. In this paper we present an ATPG based delay test methodology to target a key class of such hazard activated open faults that are not detected by traditional stuck open tests. Through detailed SPICE simulations, we show that the detected open defects can in fact be activated by such tests and therefore result in erroneous outputs in normal functional operation.

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Section: Background and Prior Workmentioning

confidence: 99%

Improving CMOS open defect coverage using hazard activated tests

Han

Singh

2014

2014 IEEE 32nd VLSI Test Symposium (VTS)

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“…A recent industrial study [1] There has been research on testing open defects reported in the literature going back many decades. Some more recent papers [3,4] have been proposed enhancing the open defect coverage of TDF test to also target the transistor stuck-open faults (TSOFs) by adding the constraint to the ATPG to additionally require gate output initialization when targeting TDFs at gate input nodes. However, the open fault coverage improvement from this approach appears limited, as a large number of TSOFs remain undetectable.…”

Section: Introductionmentioning

confidence: 99%

Testing cross wire opens within complex gates

Han

Singh

2015

2015 IEEE 33rd VLSI Test Symposium (VTS)

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Recent test studies on volume production data suggest that a significant number of CMOS open defects remain undetected by commonly applied TDF timing tests, potentially leading to high defectivity in the shipped parts. This has focused attention on developing tests that explicitly target open faults, in particular transistor stuck open faults (TSOFs). However, while TSOFs cover all open faults in circuits implemented from primitive logic gates, they do not model a type of open fault found only in complex CMOS gates. We refer to these as cross wire open (CWO) faults. In this paper, we develop the first tests that target CWOs. Although we observe that the fault list of potential CWOs can be significantly reduced if the layouts of complex gate cells used in the design are available, we present test generation methodologies both with and without this layout information. CWO fault coverage results for scan based tests are presented for ISCAS89 and ITC99 benchmark circuits that have been resynthesized using an open source cell library containing complex gates.

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“…Hillebrecht et al [8] developed a flow that integrates the physical information (including the layout and the cell library) and the aggressor -victim model for pattern generation. Devtaprasanna et al [9] gave a solution of testing intra-gate open defects and obtained the complete defect coverage. Gomez et al [10] used the commercial tool to build a flow from layout extraction to Automatic Test Pattern Generation (ATPG) for interconnect open defect.…”

Section: Introductionmentioning

confidence: 99%

Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow

Chen

Chang

Wen

2012

IET Comput. Digit. Tech.

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As an open defect occurs in one wire segment of the circuit, different logic values on the coupling wires of the physical layout may result in different faulty behaviours, which are so called the Byzantine effect. Many previous researches focus on the test and diagnosis of open defects but the pattern diagnosability has not properly addressed. Therefore in this study, a highresolution diagnostic framework for open defects is proposed and consists of a diagnostic test-pattern generation (DTPG) and its diagnosis flow. The branch-and-bound search associated with controllability analysis is incorporated in satisfiability-based DTPG to generate patterns for the target segment. Later, a precise diagnosis flow constructs the list of defect candidates in a dictionary-based fashion followed by an inject-and-evaluate analysis to greatly reduce the number of candidates for silicon inspection. Experimental results show that the proposed framework runs efficiently and deduces nearly one candidate for each open-segment defect on average among all ISCAS'85 benchmark circuits.

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Test Generation for Open Defects in CMOS Circuits

Cited by 13 publications

References 22 publications

Improving CMOS open defect coverage using hazard activated tests

Improving CMOS open defect coverage using hazard activated tests

Testing cross wire opens within complex gates

Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow

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