Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals

Ogihara, Takuji; Murai, Shinichi; Takamatsu, Y.; Kinoshita, Kento; Fujiwara, Haruo

doi:10.1109/dac.1983.1585628

Cited by 20 publications

(7 citation statements)

References 3 publications

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“…The drawbacks of the well-known algorithms of PO-DEM [17] and FAN [16] for circuits with tristate devices have been well reported in the literature [12,26,27,31,34,37]. Since tristate devices can float, most of these algorithms use a new logic value (Z ) to denote an output different from the traditional binary values of 0 and 1.…”

Section: Previous Workmentioning

confidence: 99%

Modeling Custom Digital Circuits for Test

Bose

2004

J Electron Test

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Models meant for logic verification and simulation are often used for Automatic Test Pattern Generation (ATPG). For custom digital circuits, these models contain many tristate devices that tend to lower coverage for stuckfaults. Additionally, these tristate devices contribute to increased ATPG runtimes, fewer generated test sequences, and an overall lower test quality. The circuit under test is partitioned into channel connected sub-networks (CCSN) that consist of transistors that are connected at their source or drain terminals, except when these terminals are power, ground or primary inputs. Unlike other published work, algorithms presented in this paper analyze each CCSN in the context of its environment, thereby capturing the logical relationships among its input signals. Other algorithms presented include identification and modeling of embedded latches, clock generators and memory circuits. An abstract array model for memory that reduces the size of the model and increases simulation speed is also presented. When one specific feature of the algorithm was disabled, experimental results showed higher ATPG runtimes of about 35%, and an average decrease in fault coverage of around 15-20%. For the largest data cache, the memory modeling algorithm decreased the number of primitives from 1.23 million to 139 thousand.

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Section: Previous Workmentioning

confidence: 99%

Modeling Custom Digital Circuits for Test

Bose

2004

J Electron Test

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“…Unlike prior methods [2], [8], the above procedure results in a test generation algorithm that has several advantages: 1) no modifications are necessary to the heuristics used by the combinational test generator, 2) no new energy functions or satisfiability models are needed for Boolean logic gates to account for non-Boolean values, 3) complex value systems [2] are not used, and 4) only Boolean values are considered for any signal. Therefore, no sophisticated encoding of 0, 1, Z , U; and X values by several Boolean variables [4] is necessary.…”

Section: ) Non-boolean Violationmentioning

confidence: 99%

“…Therefore, if the good circuit produces a Boolean (non-Boolean) response at a particular output for any given input vector, then the faulty circuit also produces the same Boolean (non-Boolean) response at the corresponding primary output. Note that prior methods [2], [8] identify only undetectable faults which they incorrectly label as redundant. Undetectable faults that are not redundant cannot be removed to simplify logic.…”

Section: Undetectability and Redundancymentioning

confidence: 99%

“…Test generation for combinational circuits with non-Boolean primitives is significantly more complex than circuits with only Boolean primitives, due to the additional Manuscript received January 16,1996. This paper was recommended by Associate Editor T. Cheng. S. T. Chakradhar non-Boolean values [2], [8]. For example, a recent technique uses a 25-valued system for generating tests for production circuits [2].…”

Section: Introductionmentioning

confidence: 99%

“…These methods are fast and practical, and share the following similarities: 1) they represent logic values on signals by Boolean variables, 2) they construct energy functions or satisfiability expressions using these Boolean variables, and 3) they solve the energy minimization or the satisfiability problem to obtain a set of Boolean values for the variables, and this set corresponds to a test for the fault. Extending these formulations to production circuits is nontrivial for the following reasons: a) signals can assume more than two values (for example, a tristate buffer can assume the high-impedance state), and two or more Boolean variables are required to represent the additional logic values [2], [8]; b) new and more complex energy functions and satisfiability expressions have to be designed for all Boolean and non-Boolean primitives in the circuit; and c) the additional Boolean variables significantly increase the search space of the test generation problem, and this can render the new formulation impractical for large designs. The present work describes a systematic methodology for converting combinational test generation algorithms for use with production circuits.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Redundancy removal and test generation for circuits with non-Boolean primitives

Chakradhar¹,

Rotherweiler²,

Agrawal³

1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Production VLSI circuits typically consist of primitives like tristate buffers, bidirectional buffers, and bus configurations that assume non-Boolean values like the high-impedance state. We describe a systematic methodology for extending test generation algorithms that work on combinational circuits with only Boolean primitives to full-scan production circuits. Key features of the methodology are illustrated using the energy minimization based test generation algorithm for combinational circuits. The main features of our methodology that make the test generation algorithm practical for large production circuits are: 1) only one Boolean variable is used to represent the value on a signal and all signals assume only Boolean values during the test generation procedure; 2) the function of non-Boolean primitives is separated into Boolean and non-Boolean components with energy functions required only for the Boolean component; and 3) non-Boolean components are implicitly considered in the energy minimization procedure. In this process, no new energy functions other than the normal Boolean gate energy functions are needed. We give a method for identifying and removing redundancies in production circuits using energy minimization. The formulation is also applicable to Boolean satisfiability and BDD methods. We first use the test generation algorithm for identifying undetectable faults and then relax specific constraints in the original test generation problem by ignoring the non-Boolean components. We show that undetectability in the relaxed formulation implies redundancy. We report redundancy removal results for production VLSI circuits, ISCAS 85, and full-scan versions of the ISCAS 89 benchmark circuits.

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Power Issues During Test

Kundu

Sanyal

2009

Power-Aware Testing and Test Strategies for Low Power Devices

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Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals

Cited by 20 publications

References 3 publications

Modeling Custom Digital Circuits for Test

Modeling Custom Digital Circuits for Test

Redundancy removal and test generation for circuits with non-Boolean primitives

Power Issues During Test

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