Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits

Abstract

Pass‐transistor logic SPL has been introduced as a circuit structure to achieve lower power consumption of LSI, and its effectiveness has been confirmed. In the current study, the authors discuss a test generation method for using logic tests to detect stuck‐on faults of pass transistors in SPL. First, the authors discuss a technique for generating a logic discrepancy (D or ˜D) between a normal circuit and a faulty circuit in an SPL circuit, and a test generation procedure using this technique. Next, they discuss a technique to solve the problem of size explosion of a table, prepared in advance for this technique in order to obtain logic values in faulty circuits. Then, the authors propose DFT (design for testability) circuits featuring very low chip surface overhead and speed overhead, to improve the fault coverage. Finally, to demonstrate its effectiveness, the method was applied to benchmark circuits. © 1999 Scripta Technica, Syst Comp Jpn, 30(7): 55–68, 1999

Wave steering to integrate logic and physical syntheses

“…We identify the single stuck-at fault controllability and observability conditions as similar to those of any PTL-mapped BDD, and we show that the entire set of such faults in a WS circuit can be mapped to a set of stuck-at faults in a PTL-mapped BDD one. Methods to test for stuck-at faults in single-ended PTL-mapped BDD circuits have been well studied in [25], while an efficient method for testing circuits derived from BDDs, which represent totally symmetric functions, was introduced in [12]. Thus, reducing the wave steering testability issues to those of PTL-mapped BDDs, which includes the special case of lattice diagrams mapped to BDDs, allows us to use the same well-established methods to test WS circuits.…”