Test methodology for embedded cores which protects intellectual property

De, K.

doi:10.1109/vtest.1997.599434

Cited by 17 publications

(15 citation statements)

References 11 publications

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“…The ATPG tool, ATA-LANTA [7], has been utilized for generating scan-stimuli and identifying scan-untestable faults. In this section, the encryption levels attained by the proposed methodology along with the comparisons against the core encryption technique in [5] are provided. Table 2 demonstrates the encryption levels achieved by the proposed scheme.…”

Section: Resultsmentioning

confidence: 99%

“…The gates ( , ) that happen to be on the propagation path for such faults can still be concealed with the insertion of an observation point (at the output of ¿); these observation points help contain the encryption degrading impact of the primary inputs. The technique we propose can be contrasted with previous techniques, such as [5], which fail to hide any of the gates for the example given in Figure 2. …”

Section: Symbolic Controllability Measures For Observation Point Insementioning

confidence: 99%

“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Encryption of soft cores has been proposed in [5]; the logic that can be tested solely through scan inputs is concealed from the core user. The approach proposed in [5] constitutes a good starting point but is rather pessimistic.…”

mentioning

confidence: 99%

“…Encryption of soft cores has been proposed in [5]; the logic that can be tested solely through scan inputs is concealed from the core user. The approach proposed in [5] constitutes a good starting point but is rather pessimistic. Not only the logic cone driving the primary outputs but furthermore the logic cone driving the pseudo-primary outputs that are reachable by any primary input are completely unveiled, resulting in the concealment of only a small set of gates in the core.…”

mentioning

confidence: 99%

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Partial core encryption for performance-efficient test of SOCs

Sinanoglu¹,

Orailoglu²

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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The isolation of a core through full I/O scan helps ease SOC test challenges; yet the performance of high-speed SOCs is significantly hampered. We propose a partial core encryption methodology wherein the core vendor unveils only a small part of the core logic, successfully satisfying core IP protection requirements. Once the partially encrypted cores are merged into an SOC, the system integrator performs test generation on the visible SOC logic only, greatly reducing the test generation effort expended. By utilizing the test data provided by the core vendor as well, the SOC integrator can test the SOC with no performance degradation. We present an efficient fault analysis based core encryption algorithm which is guided by judiciously computed testability measures. The experimental results confirm the significantly high encryption levels attained by the proposed encryption algorithm.

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Section: Resultsmentioning

confidence: 99%

Section: Symbolic Controllability Measures For Observation Point Insementioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

Partial core encryption for performance-efficient test of SOCs

Sinanoglu¹,

Orailoglu²

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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show abstract

“…Several DFT approaches were introduced to minimize the hardware cost of the serial scan ring around a core, by using existing functional flip-flops, mixing internal and external FFs, or using compaction and expansion [4] [13]. In realistic examples often a combination of serial and parallel access cells are used for a given core, where the data patterns are applied through the serial ring, whereas the clocks and control signals are asserted via parallel access.…”

Section: Serial Scan Accessmentioning

confidence: 99%

System-chip test strategies

Zorian

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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The Coupling Model for Function and Delay Faults

Hayes

2005

J Electron Test

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We propose a high-level fault model, the coupling fault (CF) model, that aims to cover both functional and timing faults in an integrated way. The basic properties of CFs and the corresponding tests are analyzed, focusing on their relationship with other fault models and their test requirements. A test generation program COTEGE for CFs is presented. Experiments with COTEGE are described which show that (reduced) coupling test sets can efficiently cover standard stuck-at-0/1 faults in a variety of different realizations. The corresponding coupling delay tests detect all robust path delay faults in any realization of a logic function.

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Test methodology for embedded cores which protects intellectual property

Cited by 17 publications

References 11 publications

Partial core encryption for performance-efficient test of SOCs

Partial core encryption for performance-efficient test of SOCs

System-chip test strategies

The Coupling Model for Function and Delay Faults

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