Test of a new sub-90-nm DR overlay mark for DRAM production

Gruss, Stefan; Teipel, Ansgar; Fuelber, Carsten; Kassel, Elyakim; Adel, Mike; Ghinovker, Mark; Izikson, Pavel

doi:10.1117/12.534518

Cited by 1 publication

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“…The integrated circuit (IC) industry is the core industry of the new generation of information technology and plays a crucial role in the national economy and security. 1 Meeting the requirements for overlay error is critical for semiconductor yield 2,3,4 , and overlay measurement equipment serves as a valuable tool for assessing photolithography process quality and yield monitoring 5,6,7 . Calibration 8,9 using double-layer gratings with specific offsets ensures accurate measurement capabilities of the overlay measurement machine 10 based on DBO overlay metrology 11,12 .…”

Section: Introductionmentioning

confidence: 99%

Analysis and simulation of spatial phase alignment for fabrication of double-layer grating

Shan,

Lu,

Deng

et al. 2023

Optical Design and Testing XIII

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During the chip manufacturing process, meeting overlay error requirements is essential to semiconductor yield. Measuring equipment of overlay error requires standard samples, which the double-layer grating with precise horizontal alignment can be used as, to verify its capability. Thus, we propose a novel alignment and processing method for layer separated processed double-layer gratings. Firstly, the bottom grating is obtained by holographic lithography . The upper and lower layers are aligned based on the homogeneous period of processing diffraction patten and the bottom grating, and manufactured simultaneously. We conducted an optical simulation of the alignment based on FDTD, setting the bottom grating as Ag material, 50 nm depth, 1μm period, and 50% duty cycle. Principally, the alignment accuracy is comparable with the linear encoder.

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