Test of Power Management Structures

Kassab, Mark; Tehranipoor, Mohammad

doi:10.1007/978-1-4419-0928-2_10

Cited by 5 publications

(1 citation statement)

References 15 publications

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“…The first design‐for‐test (DFT) solution is reported in [6] which can test switches in both fine‐grain and coarse‐grain designs. However, the first DFT solution suffers from the problem of long discharge time [7]. To decrease the long discharge time, a discharge transistor (DT) is added in the DFT circuit [8].…”

Section: Introductionmentioning

confidence: 99%

Built‐in self test design of power switch with clock‐gated charge/discharge transistor

Chen

Bai

et al. 2014

IET Computers & Digital Techniques

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It is becoming common to implement header (footer) power switches in low-power system-on-chip. However, the switches are not tested for manufacturing defects in most designs currently. In this study, a novel built-in self test (BIST) solution for power switch is proposed. To accelerate the test of the header (footer) switches, a charge (discharge) transistor is adopted in the proposed BIST circuit and the corresponding charge (discharge) transistor is gated by the test clock. Therefore the number of test patterns, the length of test vectors and the test time are all decreased. Besides, the test responses can be identified easily. If the test responses are all logic-high, the tested switches are fault-free. Or else, the tested switches are faulty. In addition, the structure of the proposed BIST circuit can be scaled freely with the amount of switches. For m switches, it takes m + 2 cycles to locate the faulty switches at worst. Finally, to verify the proposed BIST circuit, the BIST design with 255 header switches is implemented with SMIC 0.18 μm 1P6M logic process. The corresponding area is 0.043 mm 2. The simulation results show that the BIST circuit can locate the possible manufacturing defects in the switches and discharge transistors within 257 clock cycles. The corresponding consumed power is 2.04 mW when the test frequency is 20 MHz.

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Section: Introductionmentioning

confidence: 99%

Built‐in self test design of power switch with clock‐gated charge/discharge transistor

Chen

Bai

et al. 2014

IET Computers & Digital Techniques

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Test and diagnosis of power switches

Valka

Bosio

Dilillo

et al. 2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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Improved DFT for Testing Power Switches

Khursheed

Yang

Al-Hashimi

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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Abstract-Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge this is the first study that analyzes recently proposed DFT solutions for testing power switches through SPICE simulations on a number of ISCAS benchmarks and presents the following contributions. It provides evidence of long discharge time when power switches are turned-off, when testing power switches using available DFT solutions. This may either lead to false test (false-fail or false-pass) or long test time. This problem is addressed through a simple and effective DFT solution to reduce the discharge time. The proposed DFT solution has been validated through SPICE simulation and shows an improvement in discharge time of at least 28-times, based on a number of ISCAS benchmarks synthesized with a 90-nm gate library.Index Terms-Sleep transistor, power switch, leakage power management, test time overhead, DFT, design for test.

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Test of Power Management Structures

Cited by 5 publications

References 15 publications

Built‐in self test design of power switch with clock‐gated charge/discharge transistor

Built‐in self test design of power switch with clock‐gated charge/discharge transistor

Test and diagnosis of power switches

Improved DFT for Testing Power Switches

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