Test pattern generation for power supply droop faults

Abstract

In deep sub-micron VLSI chips, when several transistors in physical proximity switch simultaneously, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. As a result of lower supply voltage, transistors may slow down. Such timing faults are termed as droop faults. Modeling of droop faults and understanding their effects on the functionality and timing behavior of the circuit are yet to be fully understood. In this paper, a new model for droop faults is proposed. A simple ATPGbased procedure for stuck-at faults has been adapted to test droop faults. For validation of the methodology in combinational circuits, a set of appropriate clusters of gates is selected to cover potential droop-prone regions in a circuit. Experimental results on ISCAS-85 benchmark circuits reveal that a very high droop fault coverage can be obtained by a short sequence of test vectors.

Resistive Bridging Fault Simulation of Industrial Circuits

“…Although test generation methods for non-standard fault models do exist [3,[10][11][12][13], they do not always scale for industrial-size circuits. Hence, it is important to determine the coverage of realistic defects by the existing test pattern sets (where the test pattern sets might have been created using conventional fault models).…”

Effect of IR-Drop on Path Delay Testing Using Statistical Analysis

“…To handle possible IR-drop failures in manufacture testing, a majority of work has resorted to test pattern generation, manipulation or validation [2,4,5,6,9,10]. In [2], a method to measure the average power of at-speed test patterns was proposed.…”

“…Prior work on IR drop analysis either does not address path delay test, or has been computationally intensive [4,6,9]. Timing analysis tool should be able to handle the IR-drop delay and transfer the information to ATPG.…”

“…Note that in this work we do not attempt to target IRdrop faults by modifying ATPG, as previous work has done [2,4,6,9]. Rather, the goal is to show that our method can be applied on top of the timing analysis results earlier in the design/test flow, such that not only ATPG, but other processes can also benefit from this method.…”

Superb

“…Although test generation methods for nonstandard fault models do exist [Ferguson and Larrabee 1991;Chang et al 1999;Krsti et al 2001;Nourani et al 2005;Mitra et al 2006], they do not always scale for industrial-size circuits. Hence, it is important to determine the coverage of realistic defects by the existing test pattern sets (where the test pattern sets might have been created using conventional fault models).…”