Test platform for fault tolerant systems design properties verification

Straka, Martin; Mičulka, Lukáš; Kastil, Jan; Kotásek, Zdenĕk

doi:10.1109/ddecs.2012.6219084

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…This parameter depends on the environment. The value 100 in the equation is the average number of bits that had an effect on the correct function of one LUT in the design tested in [26]. This number is computed as the fraction between all bits that affected the design and the number of LUT in the design.…”

Section: Resultsmentioning

confidence: 99%

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Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA

Kastil

Straka

Mičulka

et al. 2012

2012 15th Euromicro Conference on Digital System Design

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In this paper, a dependability analysis of fault tolerant systems implemented into the SRAM-based FPGA is presented. The fault tolerant architectures are based on the redundancy of functional units associated with a concurrent error detection technique which uses the principles of partial dynamic reconfiguration as a recovery mechanism from a fault occurrence. Architectures are tested by injecting soft errors into partial bitstream in FPGA by an SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, for fault tolerant architecture Markov dependability models are created and how the reliability and availability parameters derived from this model for different configurations of architectures and faulty modules is demonstrated. The reliability analysis results are then shown.

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Section: Resultsmentioning

confidence: 99%

“…However, the actual number depends on the type of the implemented system and even on the setting of place and route tools. Therefore, we used the experiments done in [26] to compute the number of bits that will affect the correct behaviour of a simple system.…”

Section: Resultsmentioning

confidence: 99%