Test-point condensation in the diagnosis of digital circuits

Fox, John

doi:10.1049/piee.1977.0015

Cited by 22 publications

(5 citation statements)

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“…This structure is often used for design debugging and can help in improving the fault coverage of tests [26]. Another option is to use an XOR tree to condense the logic values at the various observation points [9,13,16,39]. Since the XOR tree requires less hardware, we use it to demonstrate an RTL DFT methodology in the next section.…”

Section: Design For Testabilitymentioning

confidence: 99%

Spectral RTL Test Generation for Microprocessors

Yogi

Agrawal

2007

20th International Conference on VLSI Design Held Jointly With 6th International Conference on Embedded Systems (VLSID'07)

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We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on inputs-outputs of the different modules/registers in the circuit, and the vectors are analyzed using Hadamard matrices for Walsh functions and the random noise level at each primary input. This information then helps generate vector sequences. At the gate-level, a fault simulator and an integer linear program (ILP) compact the test sequences. RTL test appraisal also helps reveal the hard-to-test parts of the circuit. An XOR observability tree was used to improve the testability of those parts. We give results for a simple accumulator-based processor named Parwan. The RTL spectral vectors produced higher coverage in shorter CPU times as compared to a gate-level ATPG.

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Section: Design For Testabilitymentioning

confidence: 99%

Spectral RTL Test Generation for Microprocessors

Yogi

Agrawal

2007

20th International Conference on VLSI Design Held Jointly With 6th International Conference on Embedded Systems (VLSID'07)

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“…This technique [11][24], used to improve observability, is independent of clock control, has negligible impact on timing, and is compatible with at-speed testing. …”

Section: Modeling Techniquesmentioning

confidence: 99%

Low-cost sequential ATPG with clock-control DFT

Abrarnovici¹,

Rudnick

2002

Proceedings of the 39th Conference on Design Automation - DAC '02

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We present a new clock-control DFT technique for sequential circuits, based on clock partitioning and selective clock freezing, and we use it to break the global feedback loops and to generate clock waves to test the resulting sequential circuit with self-loops. Clock waves allow us to significantly reduce the complexity of sequential ATPG. Unlike scan, our non-intrusive DFT technique does not introduce any delay penalty; the generated tests may be applied at speed, have shorter application time, and dissipate less power.Automatic test-pattern generation (ATPG) for sequential circuits is an extremely expensive computational process, so that ATPG algorithms working on complex circuits can spend many hours of CPU time and still obtain poor results in terms of fault coverage. Because of the difficulty of the sequential ATPG problem, the electronics industry has given up the idea that complex circuits can be tested without intrusive design for testability (DFT) techniques, such as scan design. However, scan-type DFT introduces delay penalties resulting in performance degradation, and scan tests require long test application times, increase the power consumption, and are difficult to run at-speed. Because many defects create delay faults, at-speed testing has become essential in achieving good defect coverage. Main ContributionsIn this paper, we introduce a new clock-control DFT technique based on clock partitioning and selective clock freezing. In a sequential circuit, a feedback loop may be local or global. A local loop includes only one flip-flop (FF) and is also called a self-loop; any loop with two or more FFs is called global. A pipeline is a loop-free (acyclic) sequential circuit. First we use clock control to temporarily freeze a subset of FFs to break all global loops; this creates a near-acyclic circuit where every FF is either feedback-free or has a self-loop; we will refer to such a circuit as a loopy pipe, since it has a pipeline structure if we ignore the self-loops. Because loopy pipes do not have global feedback, they are structurally simpler than sequential circuits with both local and global feedback. Many partial-scan design methods, starting with [6], scan FFs to break all global feedback, so that the resulting partial-scan circuit is a loopy pipe. However, sequential ATPG for a loopy pipe can still be difficult. In fact, counters, which are notoriously difficult for sequential ATPG, are often implemented by loopy pipes.A major contribution of the paper is using clock control to generate clock waves. A clock wave is a novel clocking scheme that allows a loopy pipe to be tested as a pipeline. We describe modeling techniques for loopy pipes tested with clock waves to allow combinational ATPG techniques to be used. We present a new sequential ATPG algorithm, called WAVEXPRESS, that detects most faults in a sequential circuit using combinational techniques, which are at least one order of magnitude faster than sequential ones.Our DFT technique, called CLOCKWAVE, does not introduce any delay penalty, ha...

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“…Each test input requires larger input patterns to be generated, and each test output requires more output response analysis. Observation points can be "condensed" using techniques such as those in [16], to reduce the number of test outputs. If at-speed testing is to be used, care must be taken in designing the condensation network so that the delay is not longer than a clock period.…”

Section: Test Point Insertion During Synthesismentioning

confidence: 99%

RP-SYN: synthesis of random pattern testable circuits with test point insertion

Touba

McCluskey²

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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An automated logic synthesis procedure, called RP-SYN, is described for synthesizing random pattern testable circuits. RP-SYN takes as an input a two-level description of a circuit and a constraint on the minimum fault detection probability (threshold below which faults are considered randompattern-resistant), and generates a multilevel implementation which satisfies the constraint while minimizing the literal count. RP-SYN identifies random-pattern-resistant faults and eliminates them through testability-driven factoring combined with test point insertion. By moving the task of test point insertion from the back-end into the synthesis process, RP-SYN reduces design time and enables better optimization of the resulting implementation. Results are shown for benchmark circuits which indicate that RP-SYN can generally reduce the random pattern test length by at least an order of magnitude with only a small area overhead.Index Terms-Built-in self-test (BIST), computer-aided design, design for testability, fault coverage, integrated circuit testing, logic optimization, logic synthesis, logic transformations, pseudorandom testing, random pattern testability, test points.

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Test-point condensation in the diagnosis of digital circuits

Cited by 22 publications

References 0 publications

Spectral RTL Test Generation for Microprocessors

Spectral RTL Test Generation for Microprocessors

Low-cost sequential ATPG with clock-control DFT

RP-SYN: synthesis of random pattern testable circuits with test point insertion

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