Abstract:SUMMARYThe increasing density of LSI chip circuits is causing the execution time of tests based on the full-scan design method to become problematical. In this paper, the authors propose a method of reducing the number of ATPG patterns for a full-scan designed LSI chip by inserting test points. To reduce the number of ATPG patterns, they proposed a test point insertion algorithm based on the improved fault detection probability and a test point insertion algorithm based on the improved value assignment probabi… Show more
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