Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures

Kurian, George Thomas; Rao, N. Madhusudan; Patidar, Virendra; Kamakoti, V.; Ravi, S.

doi:10.1166/jolpe.2009.1001

Journal of Low Power Electronics

2009

DOI: 10.1166/jolpe.2009.1001

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Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures

George Thomas Kurian¹,

N. Madhusudan Rao²,

Virendra Patidar³

et al.

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Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures

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