Test sequence compaction methods for acyclic sequential circuits using a time expansion model

Abstract

SUMMARYTest sequences for acyclic sequential circuits can be generated by using a time expansion model. In this paper, static and dynamic test sequence compaction techniques are proposed in which the test sequence generated by the time expansion model has two characteristics: (1) The test sequence length is constant, and (2) The location of an undefined value (X) for all primary inputs can be determined independently of test generation faults. First, a static test sequence compaction method is proposed that uses a template which is independent of the value of the test sequence. Then a dynamic test sequence compaction method is presented using reverse transform fault simulation, performing fault simulation for the time expansion model of the test pattern in which the test sequence after compaction is reverse-transformed. As a result of application of the proposed method to acyclic sequential circuits made by using partial scan design, the test sequence length was reduced by 19 to 34%.