Test structures and their application in structural testing of digital RSFQ circuits

Joseph, Arun; Heuvelmans, S.; Gerritsma, G.J.; Kerkhoff, Hans G.

doi:10.1016/j.physc.2003.12.001

Cited by 5 publications

(5 citation statements)

References 14 publications

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“…Hence, the probability of the occurrence of the predicted defects had to be determined using structures capable of detecting these defects. Our earlier work on the JeSEF Nb process had resulted in structures capable of detecting a single defect at a time [6]. Some of the structures were translated for the HYPRES process.…”

Section: Defect-prone Locations and Structures In The Hypres Promentioning

confidence: 99%

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Structural Testing of the HYPRES Niobium Process

Joseph

Sesé

Flokstra³

et al. 2005

IEEE Trans. Appl. Supercond.

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The HYPRES 3.0 m Niobium (Nb) process has proven to be capable of realizing complex Low Temperature Superconductor (LTS) Rapid Single Flux Quantum (RSFQ) circuits. In such a mature fabrication process, the importance of the detection of random defects is crucial as they contribute to the majority of the defects occurring while processing the chips. The global low yield in SCE is due to the fact that little is known about the defects and fault mechanisms occurring in Nb technology. This is, however, of crucial importance in realizing the required complex systems with yields required for commercial production. For this purpose, a structural testing approach has been applied to the HYPRES Nb process. As a result, we have developed test structures for the detection of random defects in the process. Test chips were realized in the process and measurements were carried out. Test results on the processed chips leading to defect statistics in the HYPRES Nb Process are presented in this paper.

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Section: Defect-prone Locations and Structures In The Hypres Promentioning

confidence: 99%

“…Then a short is detected if the measurement between any of the T1/T7 with T2/T3 or T5/T8 results in a measurable resistance. More details on the other types of structures used are presented in [6].…”

Section: Defect-prone Locations and Structures In The Hypres Promentioning

confidence: 99%

Structural Testing of the HYPRES Niobium Process

Joseph

Sesé

Flokstra³

et al. 2005

IEEE Trans. Appl. Supercond.

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“…Test structures were designed for the various defects listed in Table 11. More details on the test structures are given in reference [16]. Fig.…”

Section: Test Structuresmentioning

confidence: 99%

“…The information gathered from our earlier study on the faulty behavior of RSFQ circuits [16,201 was used in the experiments. We found that an introduction of 0.6 Q was enough for the complete malfunctioning of the circuit.…”

Section: 1mentioning

confidence: 99%

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Towards structural testing of superconductor electronics

Joseph

Kerkhoff

International Test Conference, 2003. Proceedings. ITC 2003.

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IntroductionRequirements for efficient new-generation electronic systems in data and telecommunication industries are pushing the semiconductor technologies to their limits. In the near future, current semiconductor technologies will not always be able to provide efficient solutions for the (now Northrop Grumman, CA) and a GHz packet switch [9] by NEC, Japan for high-speed networks.As the complexity of the circuits is increasing, the realization of the design becomes a difficult task. Although extended research is going on in making complex circuits and scaling down the minimum sizes, very little or no information is available in the literature on the methodology for defect analysis for superconductor electronics. The yield levels are currently much lower than in the semiconductor industry. This is due to the fact that while much research has been carried out with respect to the defects in semiconductor manufacturing processes [lo], little information is available on superconductor processes.In semiconductor microelectronics, special test structures have been developed and realized along with the functional integrated circuits. The information gathered using these test structures are used for yield analysis and defect-oriented testing [ 111. Fault models have been developed after studying the behaviour of the test structures. These fault models are subsequently used for ATPG and fault simulation of the circuit. In this way, the

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Data-driven fault model development for superconducting logic

Wang

Gupta

2020

2020 IEEE International Test Conference (ITC)

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Test structures and their application in structural testing of digital RSFQ circuits

Cited by 5 publications

References 14 publications

Structural Testing of the HYPRES Niobium Process

Structural Testing of the HYPRES Niobium Process

Towards structural testing of superconductor electronics

Data-driven fault model development for superconducting logic

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