Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

Kasiński, Krzysztof; Zubrzycka, W.

doi:10.1117/12.2249137

Cited by 6 publications

(6 citation statements)

References 6 publications

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“…Micropogo probe testing fixtures have been used for ASIC testing across many architectures. [10][11][12] Micropogo probes are conductive, spring-loaded contacts that make temporary connections to the NuASIC. The test socket is composed of the micropogo probes and a probe guide, which are depicted in Fig.…”

Section: Nuasics Testing Requirements and Ats Designmentioning

confidence: 99%

Testing station for fast screening of through silicon via-enabled application-specific integrated circuits for hard x-ray imaging detectors

Violette

Allen

Hong

et al. 2022

J. Astron. Telesc. Instrum. Syst.

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Application-specific integrated circuits (ASICs) are used in space-borne instruments for signal processing and detector readout. The electrical interface of these ASICs to frontend printed circuit boards is commonly accomplished with wire bonds. Through silicon via (TSV) technology has been proposed as an alternative interconnect technique that will reduce assembly complexity of ASIC packaging by replacing wire bonding with flip-chip bonding. TSV technology is advantageous in large detector arrays where TSVs enable close detector tiling on all sides. Wafer-level probe card testing of TSV ASICs is frustrated by solder balls introduced onto the ASIC surface for flip-chip bonding that hamper alignment. Therefore, we developed the ASIC test stand (ATS) to enable rapid screening and characterization of individual ASIC die. We successfully demonstrated ATS operation on ASICs originally developed for CdZnTe detectors on the Nuclear Spectroscopic and Telescope Array (NuSTAR) mission that were later modified with TSVs in a via-last process. We tested both backside blind-TSVs and frontside through-TSVs, with results from internal test pulser measurements that demonstrate performance equal to or exceeding the probe card wafer-level testing data. The ATS can easily be expanded or duplicated to parallelize ASIC screening for large area imaging detectors of future space programs.

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Section: Nuasics Testing Requirements and Ats Designmentioning

confidence: 99%

Testing station for fast screening of through silicon via-enabled application-specific integrated circuits for hard x-ray imaging detectors

Violette

Allen

Hong

et al. 2022

J. Astron. Telesc. Instrum. Syst.

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show abstract

“…Testing all produced ASICs, assembled Front End Boards (FEBs), and full modules is the essential quality verification step in the production process [6,7]. The whole testing process will include testing of approx.…”

Section: Motivation For Tester Developmentmentioning

confidence: 99%

“…The complete test procedure is relatively complex [7] and requires a possibility to control the tested ASICs from the software, receive and analyze the collected hit data.…”

Section: Motivation For Tester Developmentmentioning

confidence: 99%

SMX and front-end board tester for CBM readout chain

Zabołotny

Emschermann²,

Gumiński³

et al. 2022

J. Inst.

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The STS-MUCH-XYTER (SMX) chip is a front-end ASIC dedicated to the readout of Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the Compressed Baryonic Matter (CBM) experiment. The production of the ASIC and the front-end boards based on it is just being started and requires thorough testing to assure quality. The paper describes the SMX tester based on a standard commercial Artix-7 FPGA module with an additional simple baseboard. In the standalone configuration, the tester is controlled via IPbus and enables full functional testing of connected SMX, front-end board (FEB), or a full detector module. The software written in Python may easily be integrated with higher-level testing software.

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“…Testing all produced ASICs, assembled FEBs, and full modules is the essential quality verification step in the production process [8,9]. The SMX contains complex analog [10] and digital [11] functionality controlled via a rich set of registers accessible with a dedicated Hit Control Transfer Synchronous Protocol (HCTSP) [12].…”

Section: Motivation For Tester Developmentmentioning

confidence: 99%

“…The complete test procedure is relatively complex [9] and requires a possibility to control the tested ASICs from the software, receive and analyze the collected hit data. The simplest approach would be to use for tests a part of the full prototype readout chain.…”

Section: Motivation For Tester Developmentmentioning

confidence: 99%

SMX and front-end board tester for CBM readout chain

Zabołotny,

Emschermann,

Gumiński

et al. 2021

Preprint

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A: The SMX chip is a front-end ASIC dedicated to the readout of STS and MUCH detectors in the CBM experiment. The production of the ASIC and the front-end boards based on it is just being started and requires thorough testing to assure quality. The paper describes the SMX tester based on a standard commercial Artix-7 FPGA module with an additional simple baseboard. In the standalone configuration, the tester is controlled via IPbus and enables full functional testing of connected SMX, FEB, or a full detector module. The software written in Python may easily be integrated with higher-level testing software.

show abstract

Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

Cited by 6 publications

References 6 publications

Testing station for fast screening of through silicon via-enabled application-specific integrated circuits for hard x-ray imaging detectors

Testing station for fast screening of through silicon via-enabled application-specific integrated circuits for hard x-ray imaging detectors

SMX and front-end board tester for CBM readout chain

SMX and front-end board tester for CBM readout chain

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