Test Versus Security: Past and Present

Abstract

Cryptographic circuits need to be protected against side-channel attacks, which target their physical attributes while the cryptographic algorithm is in execution. There can be various side-channels, such as power, timing, electromagnetic radiation, fault response, and so on. One such important side-channel is the design-for-testability (DfT) infrastructure present for effective and timely testing of VLSI circuits. The attacker can extract secret information stored on the chip by scanning out test responses against some chosen plaintext inputs. The purpose of this paper is to first present a detailed survey on the state-of-the-art in scan-based side-channel attacks on symmetric and public-key cryptographic hardware implementations, both in the absence and presence of advanced DfT structures, such as test compression and X-masking, which may make the attack difficult. Then, the existing scan attack countermeasures are evaluated for determining their security against known scan attacks. In addition, JTAG vulnerability and security countermeasures are also analyzed as part of the external test interface. A comparative area-timing-security analysis of existing countermeasures at various abstraction levels is presented in order to help an embedded security designer make an informed choice for his intended application.INDEX TERMS Hardware security, scan-based attacks, test interface misuse, scan attack countermeasures, comparative area-timing-security analysis.

Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents

“…5, we can see R 3 is not SR-equivalent. We then apply step (2), and get the modified circuit R 6 that is SR equivalent as shown in Fig. 8.…”

“…In [8], we clarified the cardinality of each class of kstage GF 2 SRs and GFSRs that are SR-equivalent. Theorem 4 [8]: The cardinality of the class of k-stage SRequivalent GF 2 SRs is 2 (2 k −1) − 1.…”

“…The total number of k-stage scan-in secure GF 2 SRs that are SR-equivalent is equal to the total number of (k−1)-stage scan-in secure GF 2 SRs.…”

“…Hence, it is important to find an efficient DFT approach that satisfies both security and testability. Various approaches to secure scan design have been reported [2]. We reported a secure and testable scan design approach by using extended shift registers called "SR-equivalents" that are functionally equivalent but not structurally equivalent to shift registers [3], [4].…”

“…In [3], [4], linear structured circuits were considered. We then expanded them into non-linear structured circuits and introduced two classes of generalized shift registers (GSRs, for short) which are generalized feed-forward shift registers (GF 2 SRs, for short) [5], [6] and generalized feedback shift registers (GFSRs, for short) [7], to consider their application to secure scan design.…”