Testability Concepts for Digital ICs

Introduction to Advanced System-on-Chip Test Design and Optimization

“…Macro Test [11] and Socet [69] make use of the core-internal functional paths as TAMs. Transparent paths are created using neighboring cores.…”

“…The test access port (tap) is the connection to an external tester and for instance the test source, test source 1, and test sink, test sink 1, are implemented on-chip [158,157]. For core c 1 , CT 11 T T ={t 1 , t 2 t }, for core c 2 , CT 21 T T ={t 4 t , t 5 } and for c 3 , CT 31 T T ={t 3 }. The system in Figure 181 can be modelled as a design with test, DT = (C, R source , R sink , p k k max , T, source, sink, core, constraint, mem, bw), where: C = {c 1 , c 2 ,..., c n } is a finite set of cores where each core c i ∈C is characterized by p idle (c i ): idle power; R source = {r 1 , r 2 ,..., r p r } is a finite set of test sources; R sink = {r 1 , r 2 ,..., r q } is a finite set of test sinks; p max : maximal allowed power at any time; For each test, one test sink and one test source are required.…”

“…For instance, if the following CT 11 T T ={t 1 , t 2 t }, CT 12 T T ={t 6 }, CT 13 T T ={t 7 , t 8 , t 9 } is given for core c 1 . For instance, if the following CT 11 T T ={t 1 , t 2 t }, CT 12 T T ={t 6 }, CT 13 T T ={t 7 , t 8 , t 9 } is given for core c 1 .…”

“…The example consists of only one test source and one test sink and three cores (c 1 , c 2 , and c 3 ) where core c 1 consists of two testable units, b 11 and b 12 , core c 2 consists of two testable units, b 21 and b 22 , and core c 3 consists of two testable units, b 31 and b 32 . The testing of the testable units b 11 and b 12 at core c 1 and b 21 and b 22 core c 2 cannot be performed at the same time as the testing of b 32 . they are placed in wrappers.…”

Quality of electronic design: from architectural level to test coverage

“…In the hw domain, testability enhancement is still largely introduced during implementation, in the structural synthesis (SFT) or through structural reconfiguration. DFT techniques, namely, BoundaryScan (BS) [23], Built-In Self Test (BIST) [24] or test point insertion [25] are introduced usually only after structural synthesis. For hw/sw systems, Philips refers test point insertion as PCOs (Points of Control and Observation) [10].…”