Testability design of motor control digital signal processor

Abstract

According to architecture characteristics of the motor control digital signal processor (MCDSP), we select standard boundary scan test which is compatible with IEEE 1149.1 as main method, and full scan test as complementary method to test whole chip. Adopted self-definition address registers, data registers, control registers together, boundary scan test makes the use of the original core circuit of MCDSP, and uses MARCH B algorithm to test RAM, ROM and registers stacks, reducing the hardware expense; full scan technique establishes a single scan chain which has function of multi-chains, reducing test application time. Compared to traditional test methods, the combined methods come to a good equilibrium between hardware expense and test application time.