Testability of circuits derived from lattice diagrams

Abstract

I n this paper the testability of circuits derived from BDDs representing totally symmetric fmctions is analyzed. A test pattern generation technique is presented that has runtime linear in the size of the BDD. The result is directly applicable to circuits derived from lattice diagrams, a new design style that combines the synthesis and the layout step. Experimental results show that complete test generation for functions with more than 500 variables can be done in less than 1 CPU second.These results find direct application in the analysis of testability of LDs. Experimental results are given to demonstrate the efficiency of the approach.The paper is structured as follows: In Section 2 basic notation and definitions are reviewed. The testability results for totally symmetric functions are given in Section 3, and the application of these results to LDs is shown. Experiments are presented in Section 4 and finally the paper is summarized.

Wave steering to integrate logic and physical syntheses

“…We identify the single stuck-at fault controllability and observability conditions as similar to those of any PTL-mapped BDD, and we show that the entire set of such faults in a WS circuit can be mapped to a set of stuck-at faults in a PTL-mapped BDD one. Methods to test for stuck-at faults in single-ended PTL-mapped BDD circuits have been well studied in [25], while an efficient method for testing circuits derived from BDDs, which represent totally symmetric functions, was introduced in [12]. Thus, reducing the wave steering testability issues to those of PTL-mapped BDDs, which includes the special case of lattice diagrams mapped to BDDs, allows us to use the same well-established methods to test WS circuits.…”