Testable design verification using Petri nets

Růžička, Richard

doi:10.1109/dsd.2003.1231960

Cited by 1 publication

(2 citation statements)

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“…If it is necessary to set i mode, which is data dependent (see section 2.2), only setting of some test controller output is not enough [5,8]. Data dependent mode of the circuit element is set using data input port of the element and it is evident that circuit controller is not been able to control values on data ports inside the circuit.…”

Section: Path Enabling Automatonmentioning

confidence: 99%

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Formal approach to synthesis of a test controller

Růžička

Tupec

Proceedings. 11th IEEE International Conference and Workshop on the Engineering of Computer-Based Systems, 2004.

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In the paper, a method for formal construction of a test controller of the RT level digital circuit is presented. As input, a digital circuit structure at RT level designed using any DfT technique is assumed. The proposed method enables to create a Finite State Machine with output, which can control all enable, address and clock inputs of circuit elements during the test application process. It is assumed that test patterns are inserted to circuit primary input ports and transferred through the circuit structure to selected points inside the circuit, to which they must be applied. Responses to these test patterns must then be transferred outside of the circuit and analyzed. Transfers of such diagnostic data are controlled by the test controller. Formal tools and approaches are used. The main advantage of formally described methods is that all processes are easily provable and no large evaluation of proposed methods on benchmark circuits is necessary.

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Section: Path Enabling Automatonmentioning

confidence: 99%

“…To develop the methodology, formal tools were used [2], [3], [5], [8]. It allows to create a formal model of a circuit, to describe its diagnostic and testability properties and describe testability analysis algorithms, all of them formally.…”

Section: Introductionmentioning

confidence: 99%

Formal approach to synthesis of a test controller

Růžička

Tupec

Proceedings. 11th IEEE International Conference and Workshop on the Engineering of Computer-Based Systems, 2004.

Self Cite

View full text Add to dashboard Cite

show abstract

Testable design verification using Petri nets

Cited by 1 publication

References 5 publications

Formal approach to synthesis of a test controller

Formal approach to synthesis of a test controller

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