TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm

Mrugalski, Grzegorz; Rajski, J.; Solecki, Jĕdrzej; Tyszer, Jerzy; Wang, Chen

doi:10.1109/ats.2015.11

Cited by 4 publications

(1 citation statement)

References 13 publications

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“…Other approaches try to increase the flexibility of the flip-flops and scan chains in the design to control and capture data during test. For example, a test-per-clock approach was proposed in [35] that adds a multiplexer and XOR gate to every flip-flop in the design so that different chains may be in one of three modes during test: stimulus, compaction, or mission mode.…”

Section: Introductionmentioning

confidence: 99%

Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift

et al. 2023

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Test sets that target standard fault models may not always be sufficient for detecting all defects. To evaluate test sets for the detection of unmodeled defects, n-detect test sets (which detect all modeled faults at least n times) have previously been proposed. Unfortunately, n-detect test sets are often prohibitively long. In this paper, we investigate the ability of shadow flip-flops connected into a MISR (Multiple Input Signature Register) to detect stuck-at faults fortuitously multiple times during scan shift. We explore which flip-flops should be shadowed to increase the value of n for the least detected stuck-at faults for each circuit studied. We then identify which circuit characteristics are most important for determining the cost of the MISR needed to achieve high values of n. For example, circuits that contain a few flip-flops with upstream fault cones that cover a large percentage of all faults in the circuit can often achieve high n-detect coverage fortuitously with a low-cost MISR. This allows a DFT engineer to predict the viability of this MISR-based approach early in the design cycle.

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Section: Introductionmentioning

confidence: 99%